ARM: socfpga: dts: Add div-reg to the main_pll clocks

The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a
pre-divider. Update socfpga.dtsi to represent those dividers for these
clocks.

Re-use the "div-reg" property that was used for the socfpga-gate-clock as this
is the same thing. Also update the documentation.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
This commit is contained in:
Dinh Nguyen 2014-04-16 15:05:15 -05:00
parent 16fb4f8bd5
commit 8cb289ed60
2 changed files with 5 additions and 5 deletions

View File

@ -21,8 +21,8 @@ Optional properties:
- fixed-divider : If clocks have a fixed divider value, use this property.
- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
and the bit index.
- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
and width.
- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
the divider register, bit shift, and width.
- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct

View File

@ -148,7 +148,7 @@
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
fixed-divider = <2>;
div-reg = <0xe0 0 9>;
reg = <0x48>;
};
@ -156,7 +156,7 @@
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
fixed-divider = <4>;
div-reg = <0xe4 0 9>;
reg = <0x4C>;
};
@ -164,7 +164,7 @@
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
fixed-divider = <4>;
div-reg = <0xe8 0 9>;
reg = <0x50>;
};