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drm/i915: remove ironlake bits from lpt_pch_enable
Since this function will only run on Haswell/LPT and newer. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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parent
303b81e040
commit
8c52b5e855
@ -3170,7 +3170,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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u32 reg, temp;
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assert_transcoder_disabled(dev_priv, pipe);
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@ -3191,34 +3190,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
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* enable sequence. */
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intel_enable_pch_pll(intel_crtc);
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if (HAS_PCH_LPT(dev)) {
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DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
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lpt_program_iclkip(crtc);
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} else if (HAS_PCH_CPT(dev)) {
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u32 sel;
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temp = I915_READ(PCH_DPLL_SEL);
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switch (pipe) {
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default:
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case 0:
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temp |= TRANSA_DPLL_ENABLE;
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sel = TRANSA_DPLLB_SEL;
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break;
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case 1:
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temp |= TRANSB_DPLL_ENABLE;
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sel = TRANSB_DPLLB_SEL;
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break;
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case 2:
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temp |= TRANSC_DPLL_ENABLE;
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sel = TRANSC_DPLLB_SEL;
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break;
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}
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if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
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temp |= sel;
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else
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temp &= ~sel;
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I915_WRITE(PCH_DPLL_SEL, temp);
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}
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lpt_program_iclkip(crtc);
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/* set transcoder timing, panel must allow it */
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assert_panel_unlocked(dev_priv, pipe);
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@ -3231,45 +3203,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
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I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
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I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
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if (!IS_HASWELL(dev))
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intel_fdi_normal_train(crtc);
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/* For PCH DP, enable TRANS_DP_CTL */
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if (HAS_PCH_CPT(dev) &&
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(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
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intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
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u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
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reg = TRANS_DP_CTL(pipe);
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temp = I915_READ(reg);
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temp &= ~(TRANS_DP_PORT_SEL_MASK |
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TRANS_DP_SYNC_MASK |
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TRANS_DP_BPC_MASK);
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temp |= (TRANS_DP_OUTPUT_ENABLE |
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TRANS_DP_ENH_FRAMING);
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temp |= bpc << 9; /* same format but at 11:9 */
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if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
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temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
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if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
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temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
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switch (intel_trans_dp_port_sel(crtc)) {
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case PCH_DP_B:
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temp |= TRANS_DP_PORT_SEL_B;
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break;
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case PCH_DP_C:
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temp |= TRANS_DP_PORT_SEL_C;
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break;
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case PCH_DP_D:
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temp |= TRANS_DP_PORT_SEL_D;
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break;
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default:
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BUG();
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}
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I915_WRITE(reg, temp);
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}
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intel_enable_transcoder(dev_priv, pipe);
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}
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