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xhci: fix event ring segment table related masks and variables in header
xHC controller can supports up to 1024 interrupters. To fit these change the max_interrupters varable from u8 to u16. Add a separate mask for the reserve and preserve bits [5:0] in the erst base register and use it instead of the ERST_PRT_MASK. ERSR_PTR_MASK [3:0] is intended for masking bits in the event ring dequeue pointer register. Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Link: https://lore.kernel.org/r/20230202150505.618915-2-mathias.nyman@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -2529,8 +2529,8 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
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"// Set ERST base address for ir_set 0 = 0x%llx",
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(unsigned long long)xhci->erst.erst_dma_addr);
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val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
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val_64 &= ERST_PTR_MASK;
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val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
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val_64 &= ERST_BASE_RSVDP;
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val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_BASE_RSVDP);
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xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
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/* Set the event ring dequeue address */
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@ -513,6 +513,9 @@ struct xhci_intr_reg {
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/* Preserve bits 16:31 of erst_size */
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#define ERST_SIZE_MASK (0xffff << 16)
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/* erst_base bitmasks */
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#define ERST_BASE_RSVDP (0x3f)
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/* erst_dequeue bitmasks */
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/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
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* where the current dequeue pointer lies. This is an optional HW hint.
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@ -1774,7 +1777,7 @@ struct xhci_hcd {
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u8 sbrn;
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u16 hci_version;
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u8 max_slots;
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u8 max_interrupters;
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u16 max_interrupters;
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u8 max_ports;
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u8 isoc_threshold;
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/* imod_interval in ns (I * 250ns) */
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