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arm: Xilinx Zynq dt patches for v3.17 third pull request
- Add Adapteva Parallella board/DT - Add SPI nodes - Add CAN nodes - Clean Zynq description -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iEYEABECAAYFAlPY12kACgkQykllyylKDCHPeACgj/z4mRSBxcFvwGyjpbSjP8LZ 7xAAn0YCK+PHYCsTcsrUOe9sdUzGFX6j =ta+s -----END PGP SIGNATURE----- Merge tag 'zynq-dt-for-3.17-3' of git://git.xilinx.com/linux-xlnx into next/dt Merge "Xilinx Zynq dt changes for v3.17 - third pull request" from Michal Simek: arm: Xilinx Zynq dt patches for v3.17 third pull request - Add Adapteva Parallella board/DT - Add SPI nodes - Add CAN nodes - Clean Zynq description * tag 'zynq-dt-for-3.17-3' of git://git.xilinx.com/linux-xlnx: ARM: zynq: DT: Clarify Xilinx Zynq platform ARM: zynq: DT: Remove DMA from board DTs ARM: zynq: DT: Add CAN node ARM: dts: zynq: Add SPI ARM: dts: zynq: Add DMAC for Parallella ARM: dts: zynq: Add Parallella device tree Documentation: devicetree: Adapteva boards Documentation: devicetree: Adapteva vendor prefix Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
8b510129ba
7
Documentation/devicetree/bindings/arm/adapteva.txt
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7
Documentation/devicetree/bindings/arm/adapteva.txt
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@ -0,0 +1,7 @@
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Adapteva Platforms Device Tree Bindings
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---------------------------------------
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Parallella board
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Required root node properties:
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- compatible = "adapteva,parallella";
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@ -1,7 +1,7 @@
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Xilinx Zynq EP107 Emulation Platform board
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Xilinx Zynq Platforms Device Tree Bindings
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This board is an emulation platform for the Zynq product which is
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based on an ARM Cortex A9 processor.
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Boards with Zynq-7000 SOC based on an ARM Cortex A9 processor
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shall have the following properties.
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Required root node properties:
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- compatible = "xlnx,zynq-ep107";
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- compatible = "xlnx,zynq-7000";
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@ -6,6 +6,7 @@ using them to avoid name-space collisions.
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abilis Abilis Systems
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active-semi Active-Semi International Inc
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ad Avionic Design GmbH
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adapteva Adapteva, Inc.
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adi Analog Devices, Inc.
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aeroflexgaisler Aeroflex Gaisler AB
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ak Asahi Kasei Corp.
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@ -458,7 +458,9 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
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wm8650-mid.dtb \
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wm8750-apc8750.dtb \
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wm8850-w70v2.dtb
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dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
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dtb-$(CONFIG_ARCH_ZYNQ) += \
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zynq-parallella.dtb \
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zynq-zc702.dtb \
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zynq-zc706.dtb \
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zynq-zed.dtb
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dtb-$(CONFIG_MACH_ARMADA_370) += \
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@ -71,7 +71,31 @@
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interrupts = <0 7 4>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 12>;
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};
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};
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can0: can@e0008000 {
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compatible = "xlnx,zynq-can-1.0";
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status = "disabled";
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clocks = <&clkc 19>, <&clkc 36>;
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clock-names = "can_clk", "pclk";
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reg = <0xe0008000 0x1000>;
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interrupts = <0 28 4>;
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interrupt-parent = <&intc>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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};
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can1: can@e0009000 {
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compatible = "xlnx,zynq-can-1.0";
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status = "disabled";
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clocks = <&clkc 20>, <&clkc 37>;
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clock-names = "can_clk", "pclk";
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reg = <0xe0009000 0x1000>;
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interrupts = <0 51 4>;
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interrupt-parent = <&intc>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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};
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gpio0: gpio@e000a000 {
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compatible = "xlnx,zynq-gpio-1.0";
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@ -140,6 +164,30 @@
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interrupts = <0 50 4>;
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};
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spi0: spi@e0006000 {
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compatible = "xlnx,zynq-spi-r1p6";
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reg = <0xe0006000 0x1000>;
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status = "disabled";
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interrupt-parent = <&intc>;
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interrupts = <0 26 4>;
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clocks = <&clkc 25>, <&clkc 34>;
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clock-names = "ref_clk", "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@e0007000 {
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compatible = "xlnx,zynq-spi-r1p6";
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reg = <0xe0007000 0x1000>;
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status = "disabled";
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interrupt-parent = <&intc>;
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interrupts = <0 49 4>;
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clocks = <&clkc 26>, <&clkc 35>;
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clock-names = "ref_clk", "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gem0: ethernet@e000b000 {
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compatible = "cdns,gem";
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reg = <0xe000b000 0x4000>;
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@ -204,6 +252,22 @@
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};
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};
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dmac_s: dmac@f8003000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xf8003000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <0 13 4>,
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<0 14 4>, <0 15 4>,
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<0 16 4>, <0 17 4>,
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<0 40 4>, <0 41 4>,
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<0 42 4>, <0 43 4>;
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <4>;
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clocks = <&clkc 27>;
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clock-names = "apb_pclk";
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};
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devcfg: devcfg@f8007000 {
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compatible = "xlnx,zynq-devcfg-1.0";
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reg = <0xf8007000 0x100>;
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64
arch/arm/boot/dts/zynq-parallella.dts
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64
arch/arm/boot/dts/zynq-parallella.dts
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/*
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* Copyright (c) 2014 SUSE LINUX Products GmbH
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*
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* Derived from zynq-zed.dts:
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*
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* Copyright (C) 2011 Xilinx
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* Copyright (C) 2012 National Instruments Corp.
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* Copyright (C) 2013 Xilinx
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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/include/ "zynq-7000.dtsi"
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/ {
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model = "Adapteva Parallella Board";
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compatible = "adapteva,parallella", "xlnx,zynq-7000";
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memory {
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device_type = "memory";
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reg = <0 0x40000000>;
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};
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chosen {
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bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
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linux,stdout-path = "/amba/serial@e0001000";
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};
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};
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&gem0 {
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy>;
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet_phy: ethernet-phy@0 {
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/* Marvell 88E1318 */
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compatible = "ethernet-phy-id0141.0e90",
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"ethernet-phy-ieee802.3-c22";
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reg = <0>;
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marvell,reg-init = <0x3 0x10 0xff00 0x1e>,
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<0x3 0x11 0xfff0 0xa>;
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};
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};
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&i2c0 {
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status = "okay";
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};
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&sdhci1 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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@ -29,6 +29,10 @@
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};
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&can0 {
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status = "okay";
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};
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&gem0 {
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status = "okay";
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phy-mode = "rgmii";
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