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net: phy: smsc: add WoL support to LAN8740/LAN8742 PHYs
Microchip LAN8740/LAN8742 PHYs support basic unicast, broadcast, and Magic Packet WoL. They have one pattern filter matching up to 128 bytes of frame data, which can be used to implement ARP or multicast WoL. ARP WoL matches any ARP frame with broadcast address. Multicast WoL matches any multicast frame. Signed-off-by: Tristram Ha <Tristram.Ha@microchip.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Simon Horman <simon.horman@corigine.com> Link: https://lore.kernel.org/r/1690329270-2873-1-git-send-email-Tristram.Ha@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Tristram Ha
Jakub Kicinski
parent
2303fae130
commit
8b305ee2a9
@ -350,6 +350,7 @@ config ROCKCHIP_PHY
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config SMSC_PHY
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tristate "SMSC PHYs"
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select CRC16
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help
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Currently supports the LAN83C185, LAN8187 and LAN8700 PHYs
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@ -20,6 +20,8 @@
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#include <linux/of.h>
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#include <linux/phy.h>
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#include <linux/netdevice.h>
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#include <linux/crc16.h>
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#include <linux/etherdevice.h>
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#include <linux/smscphy.h>
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/* Vendor-specific PHY Definitions */
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@ -51,6 +53,7 @@ struct smsc_phy_priv {
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unsigned int edpd_enable:1;
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unsigned int edpd_mode_set_by_user:1;
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unsigned int edpd_max_wait_ms;
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bool wol_arp;
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};
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static int smsc_phy_ack_interrupt(struct phy_device *phydev)
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@ -258,6 +261,243 @@ int lan87xx_read_status(struct phy_device *phydev)
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}
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EXPORT_SYMBOL_GPL(lan87xx_read_status);
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static int lan874x_phy_config_init(struct phy_device *phydev)
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{
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u16 val;
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int rc;
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/* Setup LED2/nINT/nPME pin to function as nPME. May need user option
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* to use LED1/nINT/nPME.
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*/
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val = MII_LAN874X_PHY_PME2_SET;
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/* The bits MII_LAN874X_PHY_WOL_PFDA_FR, MII_LAN874X_PHY_WOL_WUFR,
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* MII_LAN874X_PHY_WOL_MPR, and MII_LAN874X_PHY_WOL_BCAST_FR need to
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* be cleared to de-assert PME signal after a WoL event happens, but
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* using PME auto clear gets around that.
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*/
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val |= MII_LAN874X_PHY_PME_SELF_CLEAR;
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rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR,
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val);
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if (rc < 0)
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return rc;
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/* set nPME self clear delay time */
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rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_MCFGR,
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MII_LAN874X_PHY_PME_SELF_CLEAR_DELAY);
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if (rc < 0)
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return rc;
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return smsc_phy_config_init(phydev);
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}
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static void lan874x_get_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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struct smsc_phy_priv *priv = phydev->priv;
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int rc;
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wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
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WAKE_ARP | WAKE_MCAST);
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wol->wolopts = 0;
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rc = phy_read_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR);
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if (rc < 0)
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return;
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if (rc & MII_LAN874X_PHY_WOL_PFDAEN)
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wol->wolopts |= WAKE_UCAST;
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if (rc & MII_LAN874X_PHY_WOL_BCSTEN)
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wol->wolopts |= WAKE_BCAST;
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if (rc & MII_LAN874X_PHY_WOL_MPEN)
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wol->wolopts |= WAKE_MAGIC;
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if (rc & MII_LAN874X_PHY_WOL_WUEN) {
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if (priv->wol_arp)
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wol->wolopts |= WAKE_ARP;
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else
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wol->wolopts |= WAKE_MCAST;
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}
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}
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static u16 smsc_crc16(const u8 *buffer, size_t len)
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{
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return bitrev16(crc16(0xFFFF, buffer, len));
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}
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static int lan874x_chk_wol_pattern(const u8 pattern[], const u16 *mask,
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u8 len, u8 *data, u8 *datalen)
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{
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size_t i, j, k;
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int ret = 0;
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u16 bits;
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/* Pattern filtering can match up to 128 bytes of frame data. There
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* are 8 registers to program the 16-bit masks, where each bit means
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* the byte will be compared. The frame data will then go through a
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* CRC16 calculation for hardware comparison. This helper function
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* makes sure only relevant frame data are included in this
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* calculation. It provides a warning when the masks and expected
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* data size do not match.
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*/
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i = 0;
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k = 0;
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while (len > 0) {
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bits = *mask;
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for (j = 0; j < 16; j++, i++, len--) {
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/* No more pattern. */
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if (!len) {
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/* The rest of bitmap is not empty. */
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if (bits)
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ret = i + 1;
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break;
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}
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if (bits & 1)
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data[k++] = pattern[i];
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bits >>= 1;
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}
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mask++;
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}
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*datalen = k;
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return ret;
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}
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static int lan874x_set_wol_pattern(struct phy_device *phydev, u16 val,
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const u8 data[], u8 datalen,
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const u16 *mask, u8 masklen)
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{
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u16 crc, reg;
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int rc;
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/* Starting pattern offset is set before calling this function. */
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val |= MII_LAN874X_PHY_WOL_FILTER_EN;
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rc = phy_write_mmd(phydev, MDIO_MMD_PCS,
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MII_LAN874X_PHY_MMD_WOL_WUF_CFGA, val);
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if (rc < 0)
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return rc;
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crc = smsc_crc16(data, datalen);
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rc = phy_write_mmd(phydev, MDIO_MMD_PCS,
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MII_LAN874X_PHY_MMD_WOL_WUF_CFGB, crc);
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if (rc < 0)
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return rc;
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masklen = (masklen + 15) & ~0xf;
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reg = MII_LAN874X_PHY_MMD_WOL_WUF_MASK7;
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while (masklen >= 16) {
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rc = phy_write_mmd(phydev, MDIO_MMD_PCS, reg, *mask);
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if (rc < 0)
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return rc;
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reg--;
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mask++;
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masklen -= 16;
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}
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/* Clear out the rest of mask registers. */
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while (reg != MII_LAN874X_PHY_MMD_WOL_WUF_MASK0) {
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phy_write_mmd(phydev, MDIO_MMD_PCS, reg, 0);
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reg--;
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}
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return rc;
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}
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static int lan874x_set_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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struct net_device *ndev = phydev->attached_dev;
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struct smsc_phy_priv *priv = phydev->priv;
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u16 val, val_wucsr;
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u8 data[128];
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u8 datalen;
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int rc;
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/* lan874x has only one WoL filter pattern */
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if ((wol->wolopts & (WAKE_ARP | WAKE_MCAST)) ==
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(WAKE_ARP | WAKE_MCAST)) {
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phydev_info(phydev,
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"lan874x WoL supports one of ARP|MCAST at a time\n");
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return -EOPNOTSUPP;
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}
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rc = phy_read_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR);
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if (rc < 0)
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return rc;
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val_wucsr = rc;
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if (wol->wolopts & WAKE_UCAST)
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val_wucsr |= MII_LAN874X_PHY_WOL_PFDAEN;
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else
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val_wucsr &= ~MII_LAN874X_PHY_WOL_PFDAEN;
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if (wol->wolopts & WAKE_BCAST)
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val_wucsr |= MII_LAN874X_PHY_WOL_BCSTEN;
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else
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val_wucsr &= ~MII_LAN874X_PHY_WOL_BCSTEN;
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if (wol->wolopts & WAKE_MAGIC)
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val_wucsr |= MII_LAN874X_PHY_WOL_MPEN;
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else
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val_wucsr &= ~MII_LAN874X_PHY_WOL_MPEN;
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/* Need to use pattern matching */
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if (wol->wolopts & (WAKE_ARP | WAKE_MCAST))
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val_wucsr |= MII_LAN874X_PHY_WOL_WUEN;
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else
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val_wucsr &= ~MII_LAN874X_PHY_WOL_WUEN;
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if (wol->wolopts & WAKE_ARP) {
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const u8 pattern[2] = { 0x08, 0x06 };
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const u16 mask[1] = { 0x0003 };
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rc = lan874x_chk_wol_pattern(pattern, mask, 2, data,
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&datalen);
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if (rc)
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phydev_dbg(phydev, "pattern not valid at %d\n", rc);
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/* Need to match broadcast destination address and provided
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* data pattern at offset 12.
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*/
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val = 12 | MII_LAN874X_PHY_WOL_FILTER_BCSTEN;
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rc = lan874x_set_wol_pattern(phydev, val, data, datalen, mask,
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2);
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if (rc < 0)
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return rc;
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priv->wol_arp = true;
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}
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if (wol->wolopts & WAKE_MCAST) {
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/* Need to match multicast destination address. */
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val = MII_LAN874X_PHY_WOL_FILTER_MCASTTEN;
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rc = lan874x_set_wol_pattern(phydev, val, data, 0, NULL, 0);
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if (rc < 0)
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return rc;
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priv->wol_arp = false;
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}
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if (wol->wolopts & (WAKE_MAGIC | WAKE_UCAST)) {
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const u8 *mac = (const u8 *)ndev->dev_addr;
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int i, reg;
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reg = MII_LAN874X_PHY_MMD_WOL_RX_ADDRC;
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for (i = 0; i < 6; i += 2, reg--) {
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rc = phy_write_mmd(phydev, MDIO_MMD_PCS, reg,
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((mac[i + 1] << 8) | mac[i]));
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if (rc < 0)
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return rc;
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}
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}
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rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR,
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val_wucsr);
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if (rc < 0)
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return rc;
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return 0;
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}
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static int smsc_get_sset_count(struct phy_device *phydev)
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{
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return ARRAY_SIZE(smsc_hw_stats);
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@ -533,7 +773,7 @@ static struct phy_driver smsc_phy_driver[] = {
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/* basic functions */
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.read_status = lan87xx_read_status,
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.config_init = smsc_phy_config_init,
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.config_init = lan874x_phy_config_init,
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.soft_reset = smsc_phy_reset,
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/* IRQ related */
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@ -548,6 +788,10 @@ static struct phy_driver smsc_phy_driver[] = {
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.get_tunable = smsc_phy_get_tunable,
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.set_tunable = smsc_phy_set_tunable,
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/* WoL */
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.set_wol = lan874x_set_wol,
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.get_wol = lan874x_get_wol,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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}, {
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@ -566,7 +810,7 @@ static struct phy_driver smsc_phy_driver[] = {
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/* basic functions */
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.read_status = lan87xx_read_status,
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.config_init = smsc_phy_config_init,
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.config_init = lan874x_phy_config_init,
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.soft_reset = smsc_phy_reset,
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/* IRQ related */
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@ -581,6 +825,10 @@ static struct phy_driver smsc_phy_driver[] = {
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.get_tunable = smsc_phy_get_tunable,
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.set_tunable = smsc_phy_set_tunable,
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/* WoL */
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.set_wol = lan874x_set_wol,
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.get_wol = lan874x_get_wol,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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} };
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@ -38,4 +38,38 @@ int smsc_phy_set_tunable(struct phy_device *phydev,
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struct ethtool_tunable *tuna, const void *data);
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int smsc_phy_probe(struct phy_device *phydev);
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#define MII_LAN874X_PHY_MMD_WOL_WUCSR 0x8010
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#define MII_LAN874X_PHY_MMD_WOL_WUF_CFGA 0x8011
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#define MII_LAN874X_PHY_MMD_WOL_WUF_CFGB 0x8012
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#define MII_LAN874X_PHY_MMD_WOL_WUF_MASK0 0x8021
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#define MII_LAN874X_PHY_MMD_WOL_WUF_MASK1 0x8022
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#define MII_LAN874X_PHY_MMD_WOL_WUF_MASK2 0x8023
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#define MII_LAN874X_PHY_MMD_WOL_WUF_MASK3 0x8024
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#define MII_LAN874X_PHY_MMD_WOL_WUF_MASK4 0x8025
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#define MII_LAN874X_PHY_MMD_WOL_WUF_MASK5 0x8026
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#define MII_LAN874X_PHY_MMD_WOL_WUF_MASK6 0x8027
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#define MII_LAN874X_PHY_MMD_WOL_WUF_MASK7 0x8028
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#define MII_LAN874X_PHY_MMD_WOL_RX_ADDRA 0x8061
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#define MII_LAN874X_PHY_MMD_WOL_RX_ADDRB 0x8062
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#define MII_LAN874X_PHY_MMD_WOL_RX_ADDRC 0x8063
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#define MII_LAN874X_PHY_MMD_MCFGR 0x8064
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#define MII_LAN874X_PHY_PME1_SET (2 << 13)
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#define MII_LAN874X_PHY_PME2_SET (2 << 11)
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#define MII_LAN874X_PHY_PME_SELF_CLEAR BIT(9)
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#define MII_LAN874X_PHY_WOL_PFDA_FR BIT(7)
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#define MII_LAN874X_PHY_WOL_WUFR BIT(6)
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#define MII_LAN874X_PHY_WOL_MPR BIT(5)
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#define MII_LAN874X_PHY_WOL_BCAST_FR BIT(4)
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#define MII_LAN874X_PHY_WOL_PFDAEN BIT(3)
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#define MII_LAN874X_PHY_WOL_WUEN BIT(2)
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#define MII_LAN874X_PHY_WOL_MPEN BIT(1)
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#define MII_LAN874X_PHY_WOL_BCSTEN BIT(0)
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#define MII_LAN874X_PHY_WOL_FILTER_EN BIT(15)
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#define MII_LAN874X_PHY_WOL_FILTER_MCASTTEN BIT(9)
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#define MII_LAN874X_PHY_WOL_FILTER_BCSTEN BIT(8)
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#define MII_LAN874X_PHY_PME_SELF_CLEAR_DELAY 0x1000 /* 81 milliseconds */
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#endif /* __LINUX_SMSCPHY_H__ */
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