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phy: qcom-qmp: Fix dts bindings to reflect reality

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A few patches have landed for the qcom-qmp PHY that affect how you
would write a device tree node.  ...yet the bindings weren't updated.
Let's remedy the situation and make the bindings refelect reality.

Fixes: efb05a50c9 ("phy: qcom-qmp: Add support for QMP V3 USB3 PHY")
Fixes: ac0d239936 ("phy: qcom-qmp: Add support for runtime PM")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Douglas Anderson 2018-07-06 16:31:42 -07:00 committed by Kishon Vijay Abraham I
parent 92696a89cd
commit 8b1087fa3a
1 changed files with 12 additions and 2 deletions
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14
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
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@ -12,7 +12,14 @@ Required properties:
"qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845, "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
"qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845. "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845.
- reg: offset and length of register set for PHY's common serdes block. - reg:
- For "qcom,sdm845-qmp-usb3-phy":
- index 0: address and length of register set for PHY's common serdes
block.
- named register "dp_com" (using reg-names): address and length of the
DP_COM control block.
- For all others:
- offset and length of register set for PHY's common serdes block.
- #clock-cells: must be 1 - #clock-cells: must be 1
- Phy pll outputs a bunch of clocks for Tx, Rx and Pipe - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
@ -60,7 +67,10 @@ Required nodes:
Required properties for child node: Required properties for child node:
- reg: list of offset and length pairs of register sets for PHY blocks - - reg: list of offset and length pairs of register sets for PHY blocks -
tx, rx and pcs. - index 0: tx
- index 1: rx
- index 2: pcs
- index 3: pcs_misc (optional)
- #phy-cells: must be 0 - #phy-cells: must be 0