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spi: nxp-fspi: switch to use modern name

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Change legacy name master/slave to modern name host/target or controller.

No functional changed.

Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20230823033003.3407403-19-yangyingliang@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Yang Yingliang 2023-08-23 11:30:00 +08:00 committed by Mark Brown
parent 2b0aa563b3
commit 8af8a27b78
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 15 additions and 15 deletions
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30
drivers/spi/spi-nxp-fspi.c
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@ -451,7 +451,7 @@ static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
static bool nxp_fspi_supports_op(struct spi_mem *mem,
const struct spi_mem_op *op)
{
struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller);
int ret;
ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth);
@ -520,7 +520,7 @@ static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
}
/*
* If the slave device content being changed by Write/Erase, need to
* If the target device content being changed by Write/Erase, need to
* invalidate the AHB buffer. This can be achieved by doing the reset
* of controller after setting MCR0[SWRESET] bit.
*/
@ -661,7 +661,7 @@ static void nxp_fspi_dll_calibration(struct nxp_fspi *f)
/*
* In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
* register and start base address of the slave device.
* register and start base address of the target device.
*
* (Higher address)
* -------- <-- FLSHB2CR0
@ -680,15 +680,15 @@ static void nxp_fspi_dll_calibration(struct nxp_fspi *f)
*
*
* Start base address defines the starting address range for given CS and
* FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS.
* FSPI_FLSHXXCR0 defines the size of the target device connected at given CS.
*
* But, different targets are having different combinations of number of CS,
* some targets only have single CS or two CS covering controller's full
* memory mapped space area.
* Thus, implementation is being done as independent of the size and number
* of the connected slave device.
* of the connected target device.
* Assign controller memory mapped space size as the size to the connected
* slave device.
* target device.
* Mark FLSHxxCR0 as zero initially and then assign value only to the selected
* chip-select Flash configuration register.
*
@ -704,8 +704,8 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi)
uint64_t size_kb;
/*
* Return, if previously selected slave device is same as current
* requested slave device.
* Return, if previously selected target device is same as current
* requested target device.
*/
if (f->selected == spi_get_chipselect(spi, 0))
return;
@ -722,7 +722,7 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi)
fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
4 * spi_get_chipselect(spi, 0));
dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi_get_chipselect(spi, 0));
dev_dbg(f->dev, "Target device [CS:%x] selected\n", spi_get_chipselect(spi, 0));
nxp_fspi_clk_disable_unprep(f);
@ -912,7 +912,7 @@ static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller);
int err = 0;
mutex_lock(&f->lock);
@ -952,7 +952,7 @@ static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
static int nxp_fspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
{
struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller);
if (op->data.dir == SPI_MEM_DATA_OUT) {
if (op->data.nbytes > f->devtype_data->txfifo)
@ -1049,7 +1049,7 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f)
fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
/*
* Config the DLL register to default value, enable the slave clock delay
* Config the DLL register to default value, enable the target clock delay
* line delay cell override mode, and use 1 fixed delay cell in DLL delay
* chain, this is the suggested setting when clock rate < 100MHz.
*/
@ -1062,7 +1062,7 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f)
base + FSPI_MCR0);
/*
* Disable same device enable bit and configure all slave devices
* Disable same device enable bit and configure all target devices
* independently.
*/
reg = fspi_readl(f, f->iobase + FSPI_MCR2);
@ -1100,7 +1100,7 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f)
static const char *nxp_fspi_get_name(struct spi_mem *mem)
{
struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller);
struct device *dev = &mem->spi->dev;
const char *name;
@ -1137,7 +1137,7 @@ static int nxp_fspi_probe(struct platform_device *pdev)
int ret;
u32 reg;
ctlr = spi_alloc_master(&pdev->dev, sizeof(*f));
ctlr = spi_alloc_host(&pdev->dev, sizeof(*f));
if (!ctlr)
return -ENOMEM;