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ARM: davinci: clk: add set_parent callback for mux clocks
Introduce a set_parent callback that will be used for mux clocks, such as the USB PHY muxes and the async3 clock domain mux. Signed-off-by: David Lechner <david@lechnology.com> [nsekhar@ti.com: checkpatch fixes] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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@ -195,6 +195,14 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
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return -EINVAL;
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mutex_lock(&clocks_mutex);
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if (clk->set_parent) {
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int ret = clk->set_parent(clk, parent);
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if (ret) {
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mutex_unlock(&clocks_mutex);
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return ret;
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}
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}
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clk->parent = parent;
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list_del_init(&clk->childnode);
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list_add(&clk->childnode, &clk->parent->children);
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@ -224,8 +232,17 @@ int clk_register(struct clk *clk)
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mutex_lock(&clocks_mutex);
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list_add_tail(&clk->node, &clocks);
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if (clk->parent)
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if (clk->parent) {
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if (clk->set_parent) {
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int ret = clk->set_parent(clk, clk->parent);
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if (ret) {
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mutex_unlock(&clocks_mutex);
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return ret;
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}
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}
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list_add_tail(&clk->childnode, &clk->parent->children);
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}
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mutex_unlock(&clocks_mutex);
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/* If rate is already set, use it */
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@ -106,6 +106,7 @@ struct clk {
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int (*reset) (struct clk *clk, bool reset);
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void (*clk_enable) (struct clk *clk);
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void (*clk_disable) (struct clk *clk);
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int (*set_parent) (struct clk *clk, struct clk *parent);
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};
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/* Clock flags: SoC-specific flags start at BIT(16) */
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