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drm/i915: Set up the documented clock gating on Sandybridge and Ironlake.
Signed-off-by: Eric Anholt <eric@anholt.net>
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8956c8bba5
drivers/gpu/drm/i915
@ -2176,6 +2176,14 @@
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#define DISPLAY_PORT_PLL_BIOS_1 0x46010
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#define DISPLAY_PORT_PLL_BIOS_2 0x46014
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#define PCH_DSPCLK_GATE_D 0x42020
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# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
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# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
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#define PCH_3DCGDIS0 0x46020
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# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
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# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
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#define FDI_PLL_FREQ_CTL 0x46030
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#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
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#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
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@ -4717,6 +4717,20 @@ void intel_init_clock_gating(struct drm_device *dev)
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* specs, but enable as much else as we can.
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*/
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if (HAS_PCH_SPLIT(dev)) {
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uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
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if (IS_IRONLAKE(dev)) {
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/* Required for FBC */
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dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
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/* Required for CxSR */
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dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(PCH_3DCGDIS0,
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MARIUNIT_CLOCK_GATE_DISABLE |
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SVSMUNIT_CLOCK_GATE_DISABLE);
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}
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I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
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return;
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} else if (IS_G4X(dev)) {
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uint32_t dspclk_gate;
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