Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next into for-davem

Conflicts:
	drivers/net/wireless/rtlwifi/rtl8192se/sw.c
This commit is contained in:
John W. Linville 2012-02-06 14:26:39 -05:00
commit 8926574c4d
268 changed files with 5313 additions and 4034 deletions

View File

@ -1412,7 +1412,7 @@ F: net/ax25/
B43 WIRELESS DRIVER
M: Stefano Brivio <stefano.brivio@polimi.it>
L: linux-wireless@vger.kernel.org
L: b43-dev@lists.infradead.org (moderated for non-subscribers)
L: b43-dev@lists.infradead.org
W: http://linuxwireless.org/en/users/Drivers/b43
S: Maintained
F: drivers/net/wireless/b43/
@ -1421,6 +1421,7 @@ B43LEGACY WIRELESS DRIVER
M: Larry Finger <Larry.Finger@lwfinger.net>
M: Stefano Brivio <stefano.brivio@polimi.it>
L: linux-wireless@vger.kernel.org
L: b43-dev@lists.infradead.org
W: http://linuxwireless.org/en/users/Drivers/b43
S: Maintained
F: drivers/net/wireless/b43legacy/

View File

@ -14,8 +14,6 @@
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#define SPOFF(offset) ((offset) / sizeof(u16))
/**************************************************
* R/W ops.
**************************************************/
@ -124,10 +122,21 @@ static int bcma_sprom_valid(const u16 *sprom)
* SPROM extraction.
**************************************************/
#define SPOFF(offset) ((offset) / sizeof(u16))
#define SPEX(_field, _offset, _mask, _shift) \
bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
{
u16 v;
u16 v, o;
int i;
u16 pwr_info_offset[] = {
SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
};
BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
ARRAY_SIZE(bus->sprom.core_pwr_info));
bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
SSB_SPROM_REVISION_REV;
@ -137,72 +146,104 @@ static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
*(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
}
bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)];
SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT;
bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT;
bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT;
bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT;
SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
SSB_SPROM4_TXPID2G0_SHIFT);
SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G1,
SSB_SPROM4_TXPID2G1_SHIFT);
SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G2,
SSB_SPROM4_TXPID2G2_SHIFT);
SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G3,
SSB_SPROM4_TXPID2G3_SHIFT);
bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT;
bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT;
bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT;
bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT;
SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL0,
SSB_SPROM4_TXPID5GL0_SHIFT);
SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL1,
SSB_SPROM4_TXPID5GL1_SHIFT);
SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL2,
SSB_SPROM4_TXPID5GL2_SHIFT);
SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL3,
SSB_SPROM4_TXPID5GL3_SHIFT);
bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT;
bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT;
bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT;
bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT;
SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G0,
SSB_SPROM4_TXPID5G0_SHIFT);
SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G1,
SSB_SPROM4_TXPID5G1_SHIFT);
SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G2,
SSB_SPROM4_TXPID5G2_SHIFT);
SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G3,
SSB_SPROM4_TXPID5G3_SHIFT);
bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT;
bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT;
bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT;
bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT;
SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH0,
SSB_SPROM4_TXPID5GH0_SHIFT);
SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH1,
SSB_SPROM4_TXPID5GH1_SHIFT);
SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH2,
SSB_SPROM4_TXPID5GH2_SHIFT);
SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH3,
SSB_SPROM4_TXPID5GH3_SHIFT);
bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)];
bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)];
bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)];
bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)];
SPEX(boardflags_lo, SSB_SPROM8_BFLLO, ~0, 0);
SPEX(boardflags_hi, SSB_SPROM8_BFLHI, ~0, 0);
SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, ~0, 0);
SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, ~0, 0);
bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)];
SPEX(country_code, SSB_SPROM8_CCODE, ~0, 0);
bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
/* Extract cores power info info */
for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
o = pwr_info_offset[i];
SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
SSB_SPROM8_2G_MAXP, 0);
bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
SSB_SPROM8_5G_MAXP, 0);
SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
SSB_SPROM8_5GH_MAXP, 0);
SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
}
SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TSSIPOS,
SSB_SROM8_FEM_TSSIPOS_SHIFT);
SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_EXTPA_GAIN,
SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_PDET_RANGE,
SSB_SROM8_FEM_PDET_RANGE_SHIFT);
SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TR_ISO,
SSB_SROM8_FEM_TR_ISO_SHIFT);
SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_ANTSWLUT,
SSB_SROM8_FEM_ANTSWLUT_SHIFT);
SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TSSIPOS,
SSB_SROM8_FEM_TSSIPOS_SHIFT);
SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_EXTPA_GAIN,
SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_PDET_RANGE,
SSB_SROM8_FEM_PDET_RANGE_SHIFT);
SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TR_ISO,
SSB_SROM8_FEM_TR_ISO_SHIFT);
SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_ANTSWLUT,
SSB_SROM8_FEM_ANTSWLUT_SHIFT);
}
int bcma_sprom_get(struct bcma_bus *bus)
@ -230,6 +271,7 @@ int bcma_sprom_get(struct bcma_bus *bus)
* TODO: understand this condition and use it */
offset = (bus->chipinfo.id == 0x4331) ? BCMA_CC_SPROM :
BCMA_CC_SPROM_PCIE6;
pr_debug("SPROM offset 0x%x\n", offset);
bcma_sprom_read(bus, offset, sprom);
if (bus->chipinfo.id == 0x4331)

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@ -80,7 +80,7 @@ static bool modparam_fastchanswitch;
module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
static int ath5k_modparam_no_hw_rfkill_switch;
static bool ath5k_modparam_no_hw_rfkill_switch;
module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch,
bool, S_IRUGO);
MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state");
@ -2442,6 +2442,9 @@ ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
BIT(NL80211_IFTYPE_ADHOC) |
BIT(NL80211_IFTYPE_MESH_POINT);
/* SW support for IBSS_RSN is provided by mac80211 */
hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
/* both antennas can be configured as RX or TX */
hw->wiphy->available_antennas_tx = 0x3;
hw->wiphy->available_antennas_rx = 0x3;

View File

@ -483,6 +483,14 @@ ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
if (ath5k_modparam_nohwcrypt)
return -EOPNOTSUPP;
if (vif->type == NL80211_IFTYPE_ADHOC &&
(key->cipher == WLAN_CIPHER_SUITE_TKIP ||
key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
/* don't program group keys when using IBSS_RSN */
return -EOPNOTSUPP;
}
switch (key->cipher) {
case WLAN_CIPHER_SUITE_WEP40:
case WLAN_CIPHER_SUITE_WEP104:

View File

@ -968,8 +968,7 @@ static void ath9k_hif_usb_dealloc_urbs(struct hif_device_usb *hif_dev)
ath9k_hif_usb_dealloc_rx_urbs(hif_dev);
}
static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev,
u32 drv_info)
static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev)
{
int transfer, err;
const void *data = hif_dev->firmware->data;
@ -1000,7 +999,7 @@ static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev,
}
kfree(buf);
if (IS_AR7010_DEVICE(drv_info))
if (IS_AR7010_DEVICE(hif_dev->usb_device_id->driver_info))
firm_offset = AR7010_FIRMWARE_TEXT;
else
firm_offset = AR9271_FIRMWARE_TEXT;
@ -1021,28 +1020,18 @@ static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev,
return 0;
}
static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev, u32 drv_info)
static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev)
{
int ret, idx;
struct usb_host_interface *alt = &hif_dev->interface->altsetting[0];
struct usb_endpoint_descriptor *endp;
int ret, idx;
/* Request firmware */
ret = request_firmware(&hif_dev->firmware, hif_dev->fw_name,
&hif_dev->udev->dev);
if (ret) {
dev_err(&hif_dev->udev->dev,
"ath9k_htc: Firmware - %s not found\n", hif_dev->fw_name);
goto err_fw_req;
}
/* Download firmware */
ret = ath9k_hif_usb_download_fw(hif_dev, drv_info);
ret = ath9k_hif_usb_download_fw(hif_dev);
if (ret) {
dev_err(&hif_dev->udev->dev,
"ath9k_htc: Firmware - %s download failed\n",
hif_dev->fw_name);
goto err_fw_download;
return ret;
}
/* On downloading the firmware to the target, the USB descriptor of EP4
@ -1064,23 +1053,84 @@ static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev, u32 drv_info)
if (ret) {
dev_err(&hif_dev->udev->dev,
"ath9k_htc: Unable to allocate URBs\n");
goto err_fw_download;
return ret;
}
return 0;
err_fw_download:
release_firmware(hif_dev->firmware);
err_fw_req:
hif_dev->firmware = NULL;
return ret;
}
static void ath9k_hif_usb_dev_deinit(struct hif_device_usb *hif_dev)
{
ath9k_hif_usb_dealloc_urbs(hif_dev);
if (hif_dev->firmware)
release_firmware(hif_dev->firmware);
}
/*
* If initialization fails or the FW cannot be retrieved,
* detach the device.
*/
static void ath9k_hif_usb_firmware_fail(struct hif_device_usb *hif_dev)
{
struct device *parent = hif_dev->udev->dev.parent;
complete(&hif_dev->fw_done);
if (parent)
device_lock(parent);
device_release_driver(&hif_dev->udev->dev);
if (parent)
device_unlock(parent);
}
static void ath9k_hif_usb_firmware_cb(const struct firmware *fw, void *context)
{
struct hif_device_usb *hif_dev = context;
int ret;
if (!fw) {
dev_err(&hif_dev->udev->dev,
"ath9k_htc: Failed to get firmware %s\n",
hif_dev->fw_name);
goto err_fw;
}
hif_dev->htc_handle = ath9k_htc_hw_alloc(hif_dev, &hif_usb,
&hif_dev->udev->dev);
if (hif_dev->htc_handle == NULL) {
goto err_fw;
}
hif_dev->firmware = fw;
/* Proceed with initialization */
ret = ath9k_hif_usb_dev_init(hif_dev);
if (ret)
goto err_dev_init;
ret = ath9k_htc_hw_init(hif_dev->htc_handle,
&hif_dev->interface->dev,
hif_dev->usb_device_id->idProduct,
hif_dev->udev->product,
hif_dev->usb_device_id->driver_info);
if (ret) {
ret = -EINVAL;
goto err_htc_hw_init;
}
complete(&hif_dev->fw_done);
return;
err_htc_hw_init:
ath9k_hif_usb_dev_deinit(hif_dev);
err_dev_init:
ath9k_htc_hw_free(hif_dev->htc_handle);
release_firmware(fw);
hif_dev->firmware = NULL;
err_fw:
ath9k_hif_usb_firmware_fail(hif_dev);
}
/*
@ -1155,20 +1205,16 @@ static int ath9k_hif_usb_probe(struct usb_interface *interface,
}
usb_get_dev(udev);
hif_dev->udev = udev;
hif_dev->interface = interface;
hif_dev->device_id = id->idProduct;
hif_dev->usb_device_id = id;
#ifdef CONFIG_PM
udev->reset_resume = 1;
#endif
usb_set_intfdata(interface, hif_dev);
hif_dev->htc_handle = ath9k_htc_hw_alloc(hif_dev, &hif_usb,
&hif_dev->udev->dev);
if (hif_dev->htc_handle == NULL) {
ret = -ENOMEM;
goto err_htc_hw_alloc;
}
init_completion(&hif_dev->fw_done);
/* Find out which firmware to load */
@ -1177,29 +1223,22 @@ static int ath9k_hif_usb_probe(struct usb_interface *interface,
else
hif_dev->fw_name = FIRMWARE_AR9271;
ret = ath9k_hif_usb_dev_init(hif_dev, id->driver_info);
ret = request_firmware_nowait(THIS_MODULE, true, hif_dev->fw_name,
&hif_dev->udev->dev, GFP_KERNEL,
hif_dev, ath9k_hif_usb_firmware_cb);
if (ret) {
ret = -EINVAL;
goto err_hif_init_usb;
dev_err(&hif_dev->udev->dev,
"ath9k_htc: Async request for firmware %s failed\n",
hif_dev->fw_name);
goto err_fw_req;
}
ret = ath9k_htc_hw_init(hif_dev->htc_handle,
&interface->dev, hif_dev->device_id,
hif_dev->udev->product, id->driver_info);
if (ret) {
ret = -EINVAL;
goto err_htc_hw_init;
}
dev_info(&hif_dev->udev->dev, "ath9k_htc: USB layer initialized\n");
dev_info(&hif_dev->udev->dev, "ath9k_htc: Firmware %s requested\n",
hif_dev->fw_name);
return 0;
err_htc_hw_init:
ath9k_hif_usb_dev_deinit(hif_dev);
err_hif_init_usb:
ath9k_htc_hw_free(hif_dev->htc_handle);
err_htc_hw_alloc:
err_fw_req:
usb_set_intfdata(interface, NULL);
kfree(hif_dev);
usb_put_dev(udev);
@ -1234,9 +1273,15 @@ static void ath9k_hif_usb_disconnect(struct usb_interface *interface)
if (!hif_dev)
return;
ath9k_htc_hw_deinit(hif_dev->htc_handle, unplugged);
ath9k_htc_hw_free(hif_dev->htc_handle);
ath9k_hif_usb_dev_deinit(hif_dev);
wait_for_completion(&hif_dev->fw_done);
if (hif_dev->firmware) {
ath9k_htc_hw_deinit(hif_dev->htc_handle, unplugged);
ath9k_htc_hw_free(hif_dev->htc_handle);
ath9k_hif_usb_dev_deinit(hif_dev);
release_firmware(hif_dev->firmware);
}
usb_set_intfdata(interface, NULL);
if (!unplugged && (hif_dev->flags & HIF_USB_START))
@ -1276,8 +1321,7 @@ static int ath9k_hif_usb_resume(struct usb_interface *interface)
return ret;
if (hif_dev->firmware) {
ret = ath9k_hif_usb_download_fw(hif_dev,
htc_handle->drv_priv->ah->hw_version.usbdev);
ret = ath9k_hif_usb_download_fw(hif_dev);
if (ret)
goto fail_resume;
} else {

View File

@ -87,10 +87,11 @@ struct cmd_buf {
#define HIF_USB_START BIT(0)
struct hif_device_usb {
u16 device_id;
struct usb_device *udev;
struct usb_interface *interface;
const struct usb_device_id *usb_device_id;
const struct firmware *firmware;
struct completion fw_done;
struct htc_target *htc_handle;
struct hif_usb_tx tx;
struct usb_anchor regout_submitted;

View File

@ -741,6 +741,8 @@ static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
hw->queues = 4;
hw->channel_change_time = 5000;
hw->max_listen_interval = 10;

View File

@ -1409,6 +1409,21 @@ static int ath9k_htc_set_key(struct ieee80211_hw *hw,
if (htc_modparam_nohwcrypt)
return -ENOSPC;
if ((vif->type == NL80211_IFTYPE_ADHOC ||
vif->type == NL80211_IFTYPE_MESH_POINT) &&
(key->cipher == WLAN_CIPHER_SUITE_TKIP ||
key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
/*
* For now, disable hw crypto for the RSN IBSS group keys. This
* could be optimized in the future to use a modified key cache
* design to support per-STA RX GTK, but until that gets
* implemented, use of software crypto for group addressed
* frames is a acceptable to allow RSN IBSS to be used.
*/
return -EOPNOTSUPP;
}
mutex_lock(&priv->mutex);
ath_dbg(common, CONFIG, "Set HW Key\n");
ath9k_htc_ps_wakeup(priv);

View File

@ -340,9 +340,7 @@ static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
fastcc = false;
ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
hchan->channel, !!(hchan->channelFlags & (CHANNEL_HT40MINUS |
CHANNEL_HT40PLUS)),
fastcc);
hchan->channel, IS_CHAN_HT40(hchan), fastcc);
r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
if (r) {

View File

@ -694,7 +694,7 @@ static u8 ath_rc_get_highest_rix(struct ath_softc *sc,
return rate;
/* This should not happen */
WARN_ON(1);
WARN_ON_ONCE(1);
rate = ath_rc_priv->valid_rate_index[0];

View File

@ -559,6 +559,7 @@ int carl9170_set_hwretry_limit(struct ar9170 *ar, const u32 max_retry);
int carl9170_upload_key(struct ar9170 *ar, const u8 id, const u8 *mac,
const u8 ktype, const u8 keyidx, const u8 *keydata, const int keylen);
int carl9170_disable_key(struct ar9170 *ar, const u8 id);
int carl9170_set_mac_tpc(struct ar9170 *ar, struct ieee80211_channel *channel);
/* RX */
void carl9170_rx(struct ar9170 *ar, void *buf, unsigned int len);
@ -593,7 +594,6 @@ int carl9170_get_noisefloor(struct ar9170 *ar);
/* FW */
int carl9170_parse_firmware(struct ar9170 *ar);
int carl9170_fw_fix_eeprom(struct ar9170 *ar);
extern struct ieee80211_rate __carl9170_ratetable[];
extern int modparam_noht;

View File

@ -389,39 +389,6 @@ carl9170_find_fw_desc(struct ar9170 *ar, const __u8 *fw_data, const size_t len)
return (void *)&fw_data[scan - found];
}
int carl9170_fw_fix_eeprom(struct ar9170 *ar)
{
const struct carl9170fw_fix_desc *fix_desc = NULL;
unsigned int i, n, off;
u32 *data = (void *)&ar->eeprom;
fix_desc = carl9170_fw_find_desc(ar, FIX_MAGIC,
sizeof(*fix_desc), CARL9170FW_FIX_DESC_CUR_VER);
if (!fix_desc)
return 0;
n = (le16_to_cpu(fix_desc->head.length) - sizeof(*fix_desc)) /
sizeof(struct carl9170fw_fix_entry);
for (i = 0; i < n; i++) {
off = le32_to_cpu(fix_desc->data[i].address) -
AR9170_EEPROM_START;
if (off >= sizeof(struct ar9170_eeprom) || (off & 3)) {
dev_err(&ar->udev->dev, "Skip invalid entry %d\n", i);
continue;
}
data[off / sizeof(*data)] &=
le32_to_cpu(fix_desc->data[i].mask);
data[off / sizeof(*data)] |=
le32_to_cpu(fix_desc->data[i].value);
}
return 0;
}
int carl9170_parse_firmware(struct ar9170 *ar)
{
const struct carl9170fw_desc_head *fw_desc = NULL;

View File

@ -485,3 +485,38 @@ int carl9170_disable_key(struct ar9170 *ar, const u8 id)
return carl9170_exec_cmd(ar, CARL9170_CMD_DKEY,
sizeof(key), (u8 *)&key, 0, NULL);
}
int carl9170_set_mac_tpc(struct ar9170 *ar, struct ieee80211_channel *channel)
{
unsigned int power, chains;
if (ar->eeprom.tx_mask != 1)
chains = AR9170_TX_PHY_TXCHAIN_2;
else
chains = AR9170_TX_PHY_TXCHAIN_1;
switch (channel->band) {
case IEEE80211_BAND_2GHZ:
power = ar->power_2G_ofdm[0] & 0x3f;
break;
case IEEE80211_BAND_5GHZ:
power = ar->power_5G_leg[0] & 0x3f;
break;
default:
BUG_ON(1);
}
power = min_t(unsigned int, power, ar->hw->conf.power_level * 2);
carl9170_regwrite_begin(ar);
carl9170_regwrite(AR9170_MAC_REG_ACK_TPC,
0x3c1e | power << 20 | chains << 26);
carl9170_regwrite(AR9170_MAC_REG_RTS_CTS_TPC,
power << 5 | chains << 11 |
power << 21 | chains << 27);
carl9170_regwrite(AR9170_MAC_REG_CFEND_QOSNULL_TPC,
power << 5 | chains << 11 |
power << 21 | chains << 27);
carl9170_regwrite_finish();
return carl9170_regwrite_result();
}

View File

@ -853,11 +853,6 @@ static int carl9170_op_config(struct ieee80211_hw *hw, u32 changed)
goto out;
}
if (changed & IEEE80211_CONF_CHANGE_POWER) {
/* TODO */
err = 0;
}
if (changed & IEEE80211_CONF_CHANGE_SMPS) {
/* TODO */
err = 0;
@ -891,6 +886,12 @@ static int carl9170_op_config(struct ieee80211_hw *hw, u32 changed)
goto out;
}
if (changed & IEEE80211_CONF_CHANGE_POWER) {
err = carl9170_set_mac_tpc(ar, ar->hw->conf.channel);
if (err)
goto out;
}
out:
mutex_unlock(&ar->mutex);
return err;
@ -1796,6 +1797,9 @@ void *carl9170_alloc(size_t priv_size)
ar->noise[i] = -95; /* ATH_DEFAULT_NOISE_FLOOR */
hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
/* As IBSS Encryption is software-based, IBSS RSN is supported. */
hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
return ar;
err_nomem:
@ -1931,10 +1935,6 @@ int carl9170_register(struct ar9170 *ar)
if (err)
return err;
err = carl9170_fw_fix_eeprom(ar);
if (err)
return err;
err = carl9170_parse_eeprom(ar);
if (err)
return err;

View File

@ -1426,15 +1426,15 @@ static void carl9170_calc_ctl(struct ar9170 *ar, u32 freq, enum carl9170_bw bw)
#undef EDGES
}
static int carl9170_set_power_cal(struct ar9170 *ar, u32 freq,
enum carl9170_bw bw)
static void carl9170_set_power_cal(struct ar9170 *ar, u32 freq,
enum carl9170_bw bw)
{
struct ar9170_calibration_target_power_legacy *ctpl;
struct ar9170_calibration_target_power_ht *ctph;
u8 *ctpres;
int ntargets;
int idx, i, n;
u8 ackpower, ackchains, f;
u8 f;
u8 pwr_freqs[AR5416_MAX_NUM_TGT_PWRS];
if (freq < 3000)
@ -1523,32 +1523,6 @@ static int carl9170_set_power_cal(struct ar9170 *ar, u32 freq,
/* calc. conformance test limits and apply to ar->power*[] */
carl9170_calc_ctl(ar, freq, bw);
/* set ACK/CTS TX power */
carl9170_regwrite_begin(ar);
if (ar->eeprom.tx_mask != 1)
ackchains = AR9170_TX_PHY_TXCHAIN_2;
else
ackchains = AR9170_TX_PHY_TXCHAIN_1;
if (freq < 3000)
ackpower = ar->power_2G_ofdm[0] & 0x3f;
else
ackpower = ar->power_5G_leg[0] & 0x3f;
carl9170_regwrite(AR9170_MAC_REG_ACK_TPC,
0x3c1e | ackpower << 20 | ackchains << 26);
carl9170_regwrite(AR9170_MAC_REG_RTS_CTS_TPC,
ackpower << 5 | ackchains << 11 |
ackpower << 21 | ackchains << 27);
carl9170_regwrite(AR9170_MAC_REG_CFEND_QOSNULL_TPC,
ackpower << 5 | ackchains << 11 |
ackpower << 21 | ackchains << 27);
carl9170_regwrite_finish();
return carl9170_regwrite_result();
}
int carl9170_get_noisefloor(struct ar9170 *ar)
@ -1712,7 +1686,9 @@ int carl9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel,
if (err)
return err;
err = carl9170_set_power_cal(ar, channel->center_freq, bw);
carl9170_set_power_cal(ar, channel->center_freq, bw);
err = carl9170_set_mac_tpc(ar, channel);
if (err)
return err;

View File

@ -719,6 +719,8 @@ static void carl9170_tx_rate_tpc_chains(struct ar9170 *ar,
else
*chains = AR9170_TX_PHY_TXCHAIN_2;
}
*tpc = min_t(unsigned int, *tpc, ar->hw->conf.power_level * 2);
}
static __le32 carl9170_tx_physet(struct ar9170 *ar,

View File

@ -999,6 +999,12 @@ static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
dev->dev->write16(dev->dev, offset, value);
}
static inline void b43_maskset16(struct b43_wldev *dev, u16 offset, u16 mask,
u16 set)
{
b43_write16(dev, offset, (b43_read16(dev, offset) & mask) | set);
}
static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
{
return dev->dev->read32(dev->dev, offset);
@ -1009,6 +1015,12 @@ static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
dev->dev->write32(dev->dev, offset, value);
}
static inline void b43_maskset32(struct b43_wldev *dev, u16 offset, u32 mask,
u32 set)
{
b43_write32(dev, offset, (b43_read32(dev, offset) & mask) | set);
}
static inline void b43_block_read(struct b43_wldev *dev, void *buffer,
size_t count, u16 offset, u8 reg_width)
{

View File

@ -580,22 +580,14 @@ void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
static void b43_time_lock(struct b43_wldev *dev)
{
u32 macctl;
macctl = b43_read32(dev, B43_MMIO_MACCTL);
macctl |= B43_MACCTL_TBTTHOLD;
b43_write32(dev, B43_MMIO_MACCTL, macctl);
b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
/* Commit the write */
b43_read32(dev, B43_MMIO_MACCTL);
}
static void b43_time_unlock(struct b43_wldev *dev)
{
u32 macctl;
macctl = b43_read32(dev, B43_MMIO_MACCTL);
macctl &= ~B43_MACCTL_TBTTHOLD;
b43_write32(dev, B43_MMIO_MACCTL, macctl);
b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
/* Commit the write */
b43_read32(dev, B43_MMIO_MACCTL);
}
@ -2487,10 +2479,8 @@ static int b43_upload_microcode(struct b43_wldev *dev)
b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
/* Start the microcode PSM */
macctl = b43_read32(dev, B43_MMIO_MACCTL);
macctl &= ~B43_MACCTL_PSM_JMP0;
macctl |= B43_MACCTL_PSM_RUN;
b43_write32(dev, B43_MMIO_MACCTL, macctl);
b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
B43_MACCTL_PSM_RUN);
/* Wait for the microcode to load and respond */
i = 0;
@ -2590,10 +2580,9 @@ static int b43_upload_microcode(struct b43_wldev *dev)
return 0;
error:
macctl = b43_read32(dev, B43_MMIO_MACCTL);
macctl &= ~B43_MACCTL_PSM_RUN;
macctl |= B43_MACCTL_PSM_JMP0;
b43_write32(dev, B43_MMIO_MACCTL, macctl);
/* Stop the microcode PSM. */
b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
B43_MACCTL_PSM_JMP0);
return err;
}
@ -2708,11 +2697,8 @@ static int b43_gpio_init(struct b43_wldev *dev)
struct ssb_device *gpiodev;
u32 mask, set;
b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
& ~B43_MACCTL_GPOUTSMSK);
b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
| 0x000F);
b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
mask = 0x0000001F;
set = 0x0000000F;
@ -2800,9 +2786,7 @@ void b43_mac_enable(struct b43_wldev *dev)
dev->mac_suspended--;
B43_WARN_ON(dev->mac_suspended < 0);
if (dev->mac_suspended == 0) {
b43_write32(dev, B43_MMIO_MACCTL,
b43_read32(dev, B43_MMIO_MACCTL)
| B43_MACCTL_ENABLED);
b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
B43_IRQ_MAC_SUSPENDED);
/* Commit writes */
@ -2823,9 +2807,7 @@ void b43_mac_suspend(struct b43_wldev *dev)
if (dev->mac_suspended == 0) {
b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
b43_write32(dev, B43_MMIO_MACCTL,
b43_read32(dev, B43_MMIO_MACCTL)
& ~B43_MACCTL_ENABLED);
b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
/* force pci to flush the write */
b43_read32(dev, B43_MMIO_MACCTL);
for (i = 35; i; i--) {
@ -2931,15 +2913,10 @@ static void b43_adjust_opmode(struct b43_wldev *dev)
* so always disable it. If we want to implement PMQ,
* we need to enable it here (clear DISCPMQ) in AP mode.
*/
if (0 /* ctl & B43_MACCTL_AP */) {
b43_write32(dev, B43_MMIO_MACCTL,
b43_read32(dev, B43_MMIO_MACCTL)
& ~B43_MACCTL_DISCPMQ);
} else {
b43_write32(dev, B43_MMIO_MACCTL,
b43_read32(dev, B43_MMIO_MACCTL)
| B43_MACCTL_DISCPMQ);
}
if (0 /* ctl & B43_MACCTL_AP */)
b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
else
b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
}
static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
@ -3083,10 +3060,8 @@ static int b43_chip_init(struct b43_wldev *dev)
if (dev->dev->core_rev < 5)
b43_write32(dev, 0x010C, 0x01000000);
b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
& ~B43_MACCTL_INFRA);
b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
| B43_MACCTL_INFRA);
b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
/* Probe Response Timeout value */
/* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
@ -4564,8 +4539,6 @@ static void b43_set_pretbtt(struct b43_wldev *dev)
/* Locking: wl->mutex */
static void b43_wireless_core_exit(struct b43_wldev *dev)
{
u32 macctl;
B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
return;
@ -4576,10 +4549,8 @@ static void b43_wireless_core_exit(struct b43_wldev *dev)
b43_set_status(dev, B43_STAT_UNINIT);
/* Stop the microcode PSM. */
macctl = b43_read32(dev, B43_MMIO_MACCTL);
macctl &= ~B43_MACCTL_PSM_RUN;
macctl |= B43_MACCTL_PSM_JMP0;
b43_write32(dev, B43_MMIO_MACCTL, macctl);
b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
B43_MACCTL_PSM_JMP0);
b43_dma_free(dev);
b43_pio_free(dev);

View File

@ -85,22 +85,11 @@ static inline bool b43_nphy_ipa(struct b43_wldev *dev)
(dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
{
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
if (dev->phy.rev >= 6) {
if (dev->dev->chip_id == 47162)
return txpwrctrl_tx_gain_ipa_rev5;
return txpwrctrl_tx_gain_ipa_rev6;
} else if (dev->phy.rev >= 5) {
return txpwrctrl_tx_gain_ipa_rev5;
} else {
return txpwrctrl_tx_gain_ipa;
}
} else {
return txpwrctrl_tx_gain_ipa_5g;
}
return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
B43_NPHY_RFSEQCA_RXEN_SHIFT;
}
/**************************************************
@ -229,7 +218,7 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
reg = (i == 0) ?
B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
b43_phy_mask(dev, reg, 0xFBFF);
b43_phy_set(dev, reg, 0x400);
switch (field) {
case 0:
@ -245,7 +234,7 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
B43_NPHY_RFCTL_CMD_START);
for (j = 0; j < 100; j++) {
if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
j = 0;
break;
}
@ -264,7 +253,7 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
B43_NPHY_RFCTL_CMD_RXTX);
for (j = 0; j < 100; j++) {
if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
j = 0;
break;
}
@ -1231,12 +1220,12 @@ static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
u16 s[2];
if (dev->phy.rev >= 3) {
save_regs_phy[0] = b43_phy_read(dev,
save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
save_regs_phy[2] = b43_phy_read(dev,
B43_NPHY_RFCTL_LUT_TRSW_UP1);
save_regs_phy[1] = b43_phy_read(dev,
save_regs_phy[3] = b43_phy_read(dev,
B43_NPHY_RFCTL_LUT_TRSW_UP2);
save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
@ -1285,12 +1274,12 @@ static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
if (dev->phy.rev >= 3) {
b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
save_regs_phy[0]);
save_regs_phy[2]);
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
save_regs_phy[1]);
b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
save_regs_phy[3]);
b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
@ -1308,6 +1297,186 @@ static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
return out;
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
{
struct b43_phy_n *nphy = dev->phy.n;
u16 saved_regs_phy_rfctl[2];
u16 saved_regs_phy[13];
u16 regs_to_store[] = {
B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
B43_NPHY_RFCTL_CMD,
B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
};
u16 class;
u16 clip_state[2];
u16 clip_off[2] = { 0xFFFF, 0xFFFF };
u8 vcm_final = 0;
s8 offset[4];
s32 results[8][4] = { };
s32 results_min[4] = { };
s32 poll_results[4] = { };
u16 *rssical_radio_regs = NULL;
u16 *rssical_phy_regs = NULL;
u16 r; /* routing */
u8 rx_core_state;
u8 core, i, j;
class = b43_nphy_classifier(dev, 0, 0);
b43_nphy_classifier(dev, 7, 4);
b43_nphy_read_clip_detection(dev, clip_state);
b43_nphy_write_clip_detection(dev, clip_off);
saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
b43_nphy_rf_control_intc_override(dev, 0, 0, 7);
b43_nphy_rf_control_intc_override(dev, 1, 1, 7);
b43_nphy_rf_control_override(dev, 0x1, 0, 0, false);
b43_nphy_rf_control_override(dev, 0x2, 1, 0, false);
b43_nphy_rf_control_override(dev, 0x80, 1, 0, false);
b43_nphy_rf_control_override(dev, 0x40, 1, 0, false);
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
b43_nphy_rf_control_override(dev, 0x20, 0, 0, false);
b43_nphy_rf_control_override(dev, 0x10, 1, 0, false);
} else {
b43_nphy_rf_control_override(dev, 0x10, 0, 0, false);
b43_nphy_rf_control_override(dev, 0x20, 1, 0, false);
}
rx_core_state = b43_nphy_get_rx_core_state(dev);
for (core = 0; core < 2; core++) {
if (!(rx_core_state & (1 << core)))
continue;
r = core ? B2056_RX1 : B2056_RX0;
b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 0, 2);
b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 1, 2);
for (i = 0; i < 8; i++) {
b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
i << 2);
b43_nphy_poll_rssi(dev, 2, results[i], 8);
}
for (i = 0; i < 4; i++) {
s32 curr;
s32 mind = 40;
s32 minpoll = 249;
u8 minvcm = 0;
if (2 * core != i)
continue;
for (j = 0; j < 8; j++) {
curr = results[j][i] * results[j][i] +
results[j][i + 1] * results[j][i];
if (curr < mind) {
mind = curr;
minvcm = j;
}
if (results[j][i] < minpoll)
minpoll = results[j][i];
}
vcm_final = minvcm;
results_min[i] = minpoll;
}
b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
vcm_final << 2);
for (i = 0; i < 4; i++) {
if (core != i / 2)
continue;
offset[i] = -results[vcm_final][i];
if (offset[i] < 0)
offset[i] = -((abs(offset[i]) + 4) / 8);
else
offset[i] = (offset[i] + 4) / 8;
if (results_min[i] == 248)
offset[i] = -32;
b43_nphy_scale_offset_rssi(dev, 0, offset[i],
(i / 2 == 0) ? 1 : 2,
(i % 2 == 0) ? 0 : 1,
2);
}
}
for (core = 0; core < 2; core++) {
if (!(rx_core_state & (1 << core)))
continue;
for (i = 0; i < 2; i++) {
b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 0, i);
b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 1, i);
b43_nphy_poll_rssi(dev, i, poll_results, 8);
for (j = 0; j < 4; j++) {
if (j / 2 == core)
offset[j] = 232 - poll_results[j];
if (offset[j] < 0)
offset[j] = -(abs(offset[j] + 4) / 8);
else
offset[j] = (offset[j] + 4) / 8;
b43_nphy_scale_offset_rssi(dev, 0,
offset[2 * core], core + 1, j % 2, i);
}
}
}
b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
/* Store for future configuration */
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
} else {
rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
}
rssical_radio_regs[0] = b43_radio_read(dev, 0x602B);
rssical_radio_regs[0] = b43_radio_read(dev, 0x702B);
rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
/* Remember for which channel we store configuration */
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
nphy->rssical_chanspec_2G.center_freq = dev->phy.channel_freq;
else
nphy->rssical_chanspec_5G.center_freq = dev->phy.channel_freq;
/* End of calibration, restore configuration */
b43_nphy_classifier(dev, 7, class);
b43_nphy_write_clip_detection(dev, clip_state);
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
{
@ -1472,12 +1641,6 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
b43_nphy_reset_cca(dev);
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
{
/* TODO */
}
/*
* RSSI Calibration
* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
@ -2229,27 +2392,12 @@ static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
*/
for (i = 0; i < 2; i++) {
if (dev->phy.rev >= 3) {
if (b43_nphy_ipa(dev)) {
txgain = *(b43_nphy_get_ipa_gain_table(dev) +
txpi[i]);
} else if (b43_current_band(dev->wl) ==
IEEE80211_BAND_5GHZ) {
/* FIXME: use 5GHz tables */
txgain =
b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
} else {
if (dev->phy.rev >= 5 &&
sprom->fem.ghz5.extpa_gain == 3)
; /* FIXME: 5GHz_txgain_HiPwrEPA */
txgain =
b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
}
txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
if (dev->phy.rev >= 3)
radio_gain = (txgain >> 16) & 0x1FFFF;
} else {
txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
else
radio_gain = (txgain >> 16) & 0x1FFF;
}
if (dev->phy.rev >= 7)
dac_gain = (txgain >> 8) & 0x7;
@ -2420,55 +2568,252 @@ static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
}
/* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
{
struct b43_phy_n *nphy = dev->phy.n;
u8 idx, delta;
u8 i, stf_mode;
for (i = 0; i < 4; i++)
nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
for (stf_mode = 0; stf_mode < 4; stf_mode++) {
delta = 0;
switch (stf_mode) {
case 0:
if (dev->phy.is_40mhz && dev->phy.rev >= 5) {
idx = 68;
} else {
delta = 1;
idx = dev->phy.is_40mhz ? 52 : 4;
}
break;
case 1:
idx = dev->phy.is_40mhz ? 76 : 28;
break;
case 2:
idx = dev->phy.is_40mhz ? 84 : 36;
break;
case 3:
idx = dev->phy.is_40mhz ? 92 : 44;
break;
}
for (i = 0; i < 20; i++) {
nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
nphy->tx_power_offset[idx];
if (i == 0)
idx += delta;
if (i == 14)
idx += 1 - delta;
if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
i == 13)
idx += 1;
}
}
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
{
struct b43_phy_n *nphy = dev->phy.n;
struct ssb_sprom *sprom = dev->dev->bus_sprom;
s16 a1[2], b0[2], b1[2];
u8 idle[2];
s8 target[2];
s32 num, den, pwr;
u32 regval[64];
u16 freq = dev->phy.channel_freq;
u16 tmp;
u16 r; /* routing */
u8 i, c;
if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
b43_read32(dev, B43_MMIO_MACCTL);
udelay(1);
}
if (nphy->hang_avoid)
b43_nphy_stay_in_carrier_search(dev, true);
b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
if (dev->phy.rev >= 3)
b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
else
b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
B43_NPHY_TXPCTL_CMD_PCTLEN);
if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
if (sprom->revision < 4) {
idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
target[0] = target[1] = 52;
a1[0] = a1[1] = -424;
b0[0] = b0[1] = 5612;
b1[0] = b1[1] = -1393;
} else {
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
for (c = 0; c < 2; c++) {
idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
target[c] = sprom->core_pwr_info[c].maxpwr_2g;
a1[c] = sprom->core_pwr_info[c].pa_2g[0];
b0[c] = sprom->core_pwr_info[c].pa_2g[1];
b1[c] = sprom->core_pwr_info[c].pa_2g[2];
}
} else if (freq >= 4900 && freq < 5100) {
for (c = 0; c < 2; c++) {
idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
}
} else if (freq >= 5100 && freq < 5500) {
for (c = 0; c < 2; c++) {
idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
target[c] = sprom->core_pwr_info[c].maxpwr_5g;
a1[c] = sprom->core_pwr_info[c].pa_5g[0];
b0[c] = sprom->core_pwr_info[c].pa_5g[1];
b1[c] = sprom->core_pwr_info[c].pa_5g[2];
}
} else if (freq >= 5500) {
for (c = 0; c < 2; c++) {
idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
}
} else {
idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
target[0] = target[1] = 52;
a1[0] = a1[1] = -424;
b0[0] = b0[1] = 5612;
b1[0] = b1[1] = -1393;
}
}
/* target[0] = target[1] = nphy->tx_power_max; */
if (dev->phy.rev >= 3) {
if (sprom->fem.ghz2.tssipos)
b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
if (dev->phy.rev >= 7) {
for (c = 0; c < 2; c++) {
r = c ? 0x190 : 0x170;
if (b43_nphy_ipa(dev))
b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
}
} else {
if (b43_nphy_ipa(dev)) {
tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
b43_radio_write(dev,
B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
b43_radio_write(dev,
B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
} else {
b43_radio_write(dev,
B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
b43_radio_write(dev,
B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
}
}
}
if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
b43_read32(dev, B43_MMIO_MACCTL);
udelay(1);
}
if (dev->phy.rev >= 7) {
b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
} else {
b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
if (dev->phy.rev > 1)
b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
}
if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
b43_phy_write(dev, B43_NPHY_TXPCTL_N,
0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
B43_NPHY_TXPCTL_ITSSI_BINF);
b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
for (c = 0; c < 2; c++) {
for (i = 0; i < 64; i++) {
num = 8 * (16 * b0[c] + b1[c] * i);
den = 32768 + a1[c] * i;
pwr = max((4 * num + den / 2) / den, -8);
if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
pwr = max(pwr, target[c] + 1);
regval[i] = pwr;
}
b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
}
b43_nphy_tx_prepare_adjusted_power_table(dev);
/*
b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
*/
if (nphy->hang_avoid)
b43_nphy_stay_in_carrier_search(dev, false);
}
static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
{
struct b43_phy *phy = &dev->phy;
const u32 *table = NULL;
#if 0
TODO: b43_ntab_papd_pga_gain_delta_ipa_2*
u32 rfpwr_offset;
u8 pga_gain;
int i;
#endif
if (phy->rev >= 3) {
if (b43_nphy_ipa(dev)) {
table = b43_nphy_get_ipa_gain_table(dev);
} else {
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
if (phy->rev == 3)
table = b43_ntab_tx_gain_rev3_5ghz;
if (phy->rev == 4)
table = b43_ntab_tx_gain_rev4_5ghz;
else
table = b43_ntab_tx_gain_rev5plus_5ghz;
} else {
table = b43_ntab_tx_gain_rev3plus_2ghz;
}
}
} else {
table = b43_ntab_tx_gain_rev0_1_2;
}
table = b43_nphy_get_tx_gain_table(dev);
b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
if (phy->rev >= 3) {
#if 0
nphy->gmval = (table[0] >> 16) & 0x7000;
#endif
for (i = 0; i < 128; i++) {
pga_gain = (table[i] >> 24) & 0xF;
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
rfpwr_offset =
b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
else
rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain];
rfpwr_offset =
0; /* FIXME */
b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
rfpwr_offset);
b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
rfpwr_offset);
}
#endif
}
}
@ -3139,32 +3484,13 @@ static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
for (i = 0; i < 2; ++i) {
table = b43_nphy_get_tx_gain_table(dev);
if (dev->phy.rev >= 3) {
enum ieee80211_band band =
b43_current_band(dev->wl);
if (b43_nphy_ipa(dev)) {
table = b43_nphy_get_ipa_gain_table(dev);
} else {
if (band == IEEE80211_BAND_5GHZ) {
if (dev->phy.rev == 3)
table = b43_ntab_tx_gain_rev3_5ghz;
else if (dev->phy.rev == 4)
table = b43_ntab_tx_gain_rev4_5ghz;
else
table = b43_ntab_tx_gain_rev5plus_5ghz;
} else {
table = b43_ntab_tx_gain_rev3plus_2ghz;
}
}
target.ipa[i] = (table[index[i]] >> 16) & 0xF;
target.pad[i] = (table[index[i]] >> 20) & 0xF;
target.pga[i] = (table[index[i]] >> 24) & 0xF;
target.txgm[i] = (table[index[i]] >> 28) & 0xF;
} else {
table = b43_ntab_tx_gain_rev0_1_2;
target.ipa[i] = (table[index[i]] >> 16) & 0x3;
target.pad[i] = (table[index[i]] >> 18) & 0x3;
target.pga[i] = (table[index[i]] >> 20) & 0x7;
@ -3968,13 +4294,10 @@ static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
#endif
}
b43_write32(dev, B43_MMIO_MACCTL,
b43_read32(dev, B43_MMIO_MACCTL) &
~B43_MACCTL_GPOUTSMSK);
b43_write16(dev, B43_MMIO_GPIO_MASK,
b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
b43_write16(dev, B43_MMIO_GPIO_CONTROL,
b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
0);
if (init) {
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
@ -4110,7 +4433,7 @@ int b43_phy_initn(struct b43_wldev *dev)
b43_nphy_tx_power_ctrl(dev, false);
b43_nphy_tx_power_fix(dev);
b43_nphy_tx_power_ctl_idle_tssi(dev);
/* TODO N PHY TX Power Control Setup */
b43_nphy_tx_power_ctl_setup(dev);
b43_nphy_tx_gain_table_upload(dev);
if (nphy->phyrxchain != 3)
@ -4530,8 +4853,7 @@ static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
{
check_phyreg(dev, reg);
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16(dev, B43_MMIO_PHY_DATA,
(b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
}
static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)

View File

@ -798,6 +798,7 @@ struct b43_phy_n {
bool txpwrctrl;
bool pwg_gain_5ghz;
u8 tx_pwr_idx[2];
s8 tx_power_offset[101];
u16 adj_pwr_tbl[84];
u16 txcal_bbmult;
u16 txiqlocal_bestc[11];

View File

@ -2214,7 +2214,7 @@ static const u16 b43_ntab_antswctl2g_r3[4][32] = {
};
/* TX gain tables */
const u32 b43_ntab_tx_gain_rev0_1_2[] = {
static const u32 b43_ntab_tx_gain_rev0_1_2[] = {
0x03cc2b44, 0x03cc2b42, 0x03cc2a44, 0x03cc2a42,
0x03cc2944, 0x03c82b44, 0x03c82b42, 0x03c82a44,
0x03c82a42, 0x03c82944, 0x03c82942, 0x03c82844,
@ -2249,7 +2249,7 @@ const u32 b43_ntab_tx_gain_rev0_1_2[] = {
0x03801442, 0x03801344, 0x03801342, 0x00002b00,
};
const u32 b43_ntab_tx_gain_rev3plus_2ghz[] = {
static const u32 b43_ntab_tx_gain_rev3plus_2ghz[] = {
0x1f410044, 0x1f410042, 0x1f410040, 0x1f41003e,
0x1f41003c, 0x1f41003b, 0x1f410039, 0x1f410037,
0x1e410044, 0x1e410042, 0x1e410040, 0x1e41003e,
@ -2284,7 +2284,7 @@ const u32 b43_ntab_tx_gain_rev3plus_2ghz[] = {
0x1041003c, 0x1041003b, 0x10410039, 0x10410037,
};
const u32 b43_ntab_tx_gain_rev3_5ghz[] = {
static const u32 b43_ntab_tx_gain_rev3_5ghz[] = {
0xcff70044, 0xcff70042, 0xcff70040, 0xcff7003e,
0xcff7003c, 0xcff7003b, 0xcff70039, 0xcff70037,
0xcef70044, 0xcef70042, 0xcef70040, 0xcef7003e,
@ -2319,7 +2319,7 @@ const u32 b43_ntab_tx_gain_rev3_5ghz[] = {
0xc0f7003c, 0xc0f7003b, 0xc0f70039, 0xc0f70037,
};
const u32 b43_ntab_tx_gain_rev4_5ghz[] = {
static const u32 b43_ntab_tx_gain_rev4_5ghz[] = {
0x2ff20044, 0x2ff20042, 0x2ff20040, 0x2ff2003e,
0x2ff2003c, 0x2ff2003b, 0x2ff20039, 0x2ff20037,
0x2ef20044, 0x2ef20042, 0x2ef20040, 0x2ef2003e,
@ -2354,7 +2354,7 @@ const u32 b43_ntab_tx_gain_rev4_5ghz[] = {
0x20d2003a, 0x20d20038, 0x20d20036, 0x20d20034,
};
const u32 b43_ntab_tx_gain_rev5plus_5ghz[] = {
static const u32 b43_ntab_tx_gain_rev5plus_5ghz[] = {
0x0f62004a, 0x0f620048, 0x0f620046, 0x0f620044,
0x0f620042, 0x0f620040, 0x0f62003e, 0x0f62003c,
0x0e620044, 0x0e620042, 0x0e620040, 0x0e62003e,
@ -2389,7 +2389,7 @@ const u32 b43_ntab_tx_gain_rev5plus_5ghz[] = {
0x0062003b, 0x00620039, 0x00620037, 0x00620035,
};
const u32 txpwrctrl_tx_gain_ipa[] = {
static const u32 txpwrctrl_tx_gain_ipa[] = {
0x5ff7002d, 0x5ff7002b, 0x5ff7002a, 0x5ff70029,
0x5ff70028, 0x5ff70027, 0x5ff70026, 0x5ff70025,
0x5ef7002d, 0x5ef7002b, 0x5ef7002a, 0x5ef70029,
@ -2424,7 +2424,7 @@ const u32 txpwrctrl_tx_gain_ipa[] = {
0x50f70028, 0x50f70027, 0x50f70026, 0x50f70025,
};
const u32 txpwrctrl_tx_gain_ipa_rev5[] = {
static const u32 txpwrctrl_tx_gain_ipa_rev5[] = {
0x1ff7002d, 0x1ff7002b, 0x1ff7002a, 0x1ff70029,
0x1ff70028, 0x1ff70027, 0x1ff70026, 0x1ff70025,
0x1ef7002d, 0x1ef7002b, 0x1ef7002a, 0x1ef70029,
@ -2459,7 +2459,7 @@ const u32 txpwrctrl_tx_gain_ipa_rev5[] = {
0x10f70028, 0x10f70027, 0x10f70026, 0x10f70025,
};
const u32 txpwrctrl_tx_gain_ipa_rev6[] = {
static const u32 txpwrctrl_tx_gain_ipa_rev6[] = {
0x0ff7002d, 0x0ff7002b, 0x0ff7002a, 0x0ff70029,
0x0ff70028, 0x0ff70027, 0x0ff70026, 0x0ff70025,
0x0ef7002d, 0x0ef7002b, 0x0ef7002a, 0x0ef70029,
@ -2494,7 +2494,7 @@ const u32 txpwrctrl_tx_gain_ipa_rev6[] = {
0x00f70028, 0x00f70027, 0x00f70026, 0x00f70025,
};
const u32 txpwrctrl_tx_gain_ipa_5g[] = {
static const u32 txpwrctrl_tx_gain_ipa_5g[] = {
0x7ff70035, 0x7ff70033, 0x7ff70032, 0x7ff70031,
0x7ff7002f, 0x7ff7002e, 0x7ff7002d, 0x7ff7002b,
0x7ff7002a, 0x7ff70029, 0x7ff70028, 0x7ff70027,
@ -2529,6 +2529,11 @@ const u32 txpwrctrl_tx_gain_ipa_5g[] = {
0x70f70021, 0x70f70020, 0x70f70020, 0x70f7001f,
};
const s8 b43_ntab_papd_pga_gain_delta_ipa_2g[] = {
-114, -108, -98, -91, -84, -78, -70, -62,
-54, -46, -39, -31, -23, -15, -8, 0
};
const u16 tbl_iqcal_gainparams[2][9][8] = {
{
{ 0x000, 0, 0, 2, 0x69, 0x69, 0x69, 0x69 },
@ -2739,11 +2744,11 @@ const struct nphy_rf_control_override_rev3 tbl_rf_control_override_rev3[] = {
{ 0x0001, 0, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0002 (fls 2) */
{ 0x0002, 1, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0004 (fls 3) */
{ 0x0004, 2, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0008 (fls 4) */
{ 0x0016, 4, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0010 (fls 5) */
{ 0x0010, 4, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0010 (fls 5) */
{ 0x0020, 5, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0020 (fls 6) */
{ 0x0040, 6, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0040 (fls 7) */
{ 0x0080, 6, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0080 (fls 8) */
{ 0x0100, 7, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0100 (fls 9) */
{ 0x0080, 7, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0080 (fls 8) */
{ 0x0100, 8, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0100 (fls 9) */
{ 0x0007, 0, 0xE7, 0xF8, 0xEC, 0xFA }, /* field == 0x0200 (fls 10) */
{ 0x0070, 4, 0xE7, 0xF8, 0xEC, 0xFA }, /* field == 0x0400 (fls 11) */
{ 0xE000, 13, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0800 (fls 12) */
@ -3126,6 +3131,53 @@ void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev)
B43_WARN_ON(1);
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
{
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
if (dev->phy.rev >= 6) {
if (dev->dev->chip_id == 47162)
return txpwrctrl_tx_gain_ipa_rev5;
return txpwrctrl_tx_gain_ipa_rev6;
} else if (dev->phy.rev >= 5) {
return txpwrctrl_tx_gain_ipa_rev5;
} else {
return txpwrctrl_tx_gain_ipa;
}
} else {
return txpwrctrl_tx_gain_ipa_5g;
}
}
const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev)
{
enum ieee80211_band band = b43_current_band(dev->wl);
struct ssb_sprom *sprom = dev->dev->bus_sprom;
if (dev->phy.rev < 3)
return b43_ntab_tx_gain_rev0_1_2;
/* rev 3+ */
if ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
(dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ)) {
return b43_nphy_get_ipa_gain_table(dev);
} else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
if (dev->phy.rev == 3)
return b43_ntab_tx_gain_rev3_5ghz;
if (dev->phy.rev == 4)
return sprom->fem.ghz5.extpa_gain == 3 ?
b43_ntab_tx_gain_rev4_5ghz :
b43_ntab_tx_gain_rev4_5ghz; /* FIXME */
else
return b43_ntab_tx_gain_rev5plus_5ghz;
} else {
if (dev->phy.rev >= 5 && sprom->fem.ghz5.extpa_gain == 3)
return b43_ntab_tx_gain_rev3plus_2ghz; /* FIXME */
else
return b43_ntab_tx_gain_rev3plus_2ghz;
}
}
struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
struct b43_wldev *dev, bool ghz5, bool ext_lna)
{

View File

@ -177,16 +177,10 @@ void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset,
void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev);
void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev);
extern const u32 b43_ntab_tx_gain_rev0_1_2[];
extern const u32 b43_ntab_tx_gain_rev3plus_2ghz[];
extern const u32 b43_ntab_tx_gain_rev3_5ghz[];
extern const u32 b43_ntab_tx_gain_rev4_5ghz[];
extern const u32 b43_ntab_tx_gain_rev5plus_5ghz[];
const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev);
extern const s8 b43_ntab_papd_pga_gain_delta_ipa_2g[];
extern const u32 txpwrctrl_tx_gain_ipa[];
extern const u32 txpwrctrl_tx_gain_ipa_rev5[];
extern const u32 txpwrctrl_tx_gain_ipa_rev6[];
extern const u32 txpwrctrl_tx_gain_ipa_5g[];
extern const u16 tbl_iqcal_gainparams[2][9][8];
extern const struct nphy_txiqcal_ladder ladder_lo[];
extern const struct nphy_txiqcal_ladder ladder_iq[];

View File

@ -16,7 +16,7 @@
# CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
# common flags
subdir-ccflags-$(CONFIG_BRCMDBG) += -DBCMDBG
subdir-ccflags-$(CONFIG_BRCMDBG) += -DDEBUG
obj-$(CONFIG_BRCMUTIL) += brcmutil/
obj-$(CONFIG_BRCMFMAC) += brcmfmac/

View File

@ -15,6 +15,8 @@
*/
/* ****************** SDIO CARD Interface Functions **************************/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/export.h>

View File

@ -13,6 +13,9 @@
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/mmc/sdio.h>

View File

@ -644,9 +644,9 @@ extern char *brcmf_ifname(struct brcmf_pub *drvr, int idx);
extern int brcmf_proto_cdc_query_dcmd(struct brcmf_pub *drvr, int ifidx,
uint cmd, void *buf, uint len);
#ifdef BCMDBG
#ifdef DEBUG
extern int brcmf_write_to_file(struct brcmf_pub *drvr, const u8 *buf, int size);
#endif /* BCMDBG */
#endif /* DEBUG */
extern int brcmf_ifname2idx(struct brcmf_pub *drvr, char *name);
extern int brcmf_c_host_event(struct brcmf_pub *drvr, int *idx,

View File

@ -19,6 +19,8 @@
* For certain dcmd codes, the dongle interprets string data from the host.
******************************************************************************/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/sched.h>

View File

@ -13,6 +13,9 @@
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/sched.h>
@ -38,7 +41,7 @@
#define BRCMF_PKT_FILTER_PATTERN_FIXED_LEN \
offsetof(struct brcmf_pkt_filter_pattern_le, mask_and_pattern)
#ifdef BCMDBG
#ifdef DEBUG
static const char brcmf_version[] =
"Dongle Host Driver, version " BRCMF_VERSION_STR "\nCompiled on "
__DATE__ " at " __TIME__;
@ -133,7 +136,7 @@ bool brcmf_c_prec_enq(struct device *dev, struct pktq *q,
return p != NULL;
}
#ifdef BCMDBG
#ifdef DEBUG
static void
brcmf_c_show_host_event(struct brcmf_event_msg *event, void *event_data)
{
@ -399,10 +402,10 @@ brcmf_c_show_host_event(struct brcmf_event_msg *event, void *event_data)
p = (char *)&buf[sizeof(struct msgtrace_hdr)];
while ((s = strstr(p, "\n")) != NULL) {
*s = '\0';
printk(KERN_DEBUG"%s\n", p);
pr_debug("%s\n", p);
p = s + 1;
}
printk(KERN_DEBUG "%s\n", p);
pr_debug("%s\n", p);
/* Reset datalen to avoid display below */
datalen = 0;
@ -430,7 +433,7 @@ brcmf_c_show_host_event(struct brcmf_event_msg *event, void *event_data)
brcmf_dbg(EVENT, "\n");
}
}
#endif /* BCMDBG */
#endif /* DEBUG */
int
brcmf_c_host_event(struct brcmf_pub *drvr, int *ifidx, void *pktdata,
@ -518,9 +521,9 @@ brcmf_c_host_event(struct brcmf_pub *drvr, int *ifidx, void *pktdata,
break;
}
#ifdef BCMDBG
#ifdef DEBUG
brcmf_c_show_host_event(event, event_data);
#endif /* BCMDBG */
#endif /* DEBUG */
return 0;
}

View File

@ -32,20 +32,20 @@
#define BRCMF_BTA_VAL 0x1000
#define BRCMF_ISCAN_VAL 0x2000
#if defined(BCMDBG)
#if defined(DEBUG)
#define brcmf_dbg(level, fmt, ...) \
do { \
if (BRCMF_ERROR_VAL == BRCMF_##level##_VAL) { \
if (brcmf_msg_level & BRCMF_##level##_VAL) { \
if (net_ratelimit()) \
printk(KERN_DEBUG "%s: " fmt, \
__func__, ##__VA_ARGS__); \
pr_debug("%s: " fmt, \
__func__, ##__VA_ARGS__); \
} \
} else { \
if (brcmf_msg_level & BRCMF_##level##_VAL) { \
printk(KERN_DEBUG "%s: " fmt, \
__func__, ##__VA_ARGS__); \
pr_debug("%s: " fmt, \
__func__, ##__VA_ARGS__); \
} \
} \
} while (0)
@ -56,7 +56,7 @@ do { \
#define BRCMF_BYTES_ON() (brcmf_msg_level & BRCMF_BYTES_VAL)
#define BRCMF_GLOM_ON() (brcmf_msg_level & BRCMF_GLOM_VAL)
#else /* (defined BCMDBG) || (defined BCMDBG) */
#else /* (defined DEBUG) || (defined DEBUG) */
#define brcmf_dbg(level, fmt, ...) no_printk(fmt, ##__VA_ARGS__)
@ -66,7 +66,13 @@ do { \
#define BRCMF_BYTES_ON() 0
#define BRCMF_GLOM_ON() 0
#endif /* defined(BCMDBG) */
#endif /* defined(DEBUG) */
#define brcmf_dbg_hex_dump(test, data, len, fmt, ...) \
do { \
if (test) \
brcmu_dbg_hex_dump(data, len, fmt, ##__VA_ARGS__); \
} while (0)
extern int brcmf_msg_level;

View File

@ -14,6 +14,8 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/kthread.h>
@ -590,8 +592,8 @@ static void brcmf_ethtool_get_drvinfo(struct net_device *ndev,
sprintf(info->bus_info, "%s", dev_name(drvr->dev));
}
static struct ethtool_ops brcmf_ethtool_ops = {
.get_drvinfo = brcmf_ethtool_get_drvinfo
static const struct ethtool_ops brcmf_ethtool_ops = {
.get_drvinfo = brcmf_ethtool_get_drvinfo,
};
static int brcmf_ethtool(struct brcmf_pub *drvr, void __user *uaddr)
@ -1146,7 +1148,7 @@ int brcmf_netdev_wait_pend8021x(struct net_device *ndev)
return pend;
}
#ifdef BCMDBG
#ifdef DEBUG
int brcmf_write_to_file(struct brcmf_pub *drvr, const u8 *buf, int size)
{
int ret = 0;
@ -1180,4 +1182,4 @@ exit:
return ret;
}
#endif /* BCMDBG */
#endif /* DEBUG */

View File

@ -14,6 +14,8 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/kthread.h>
@ -40,7 +42,7 @@
#define DCMD_RESP_TIMEOUT 2000 /* In milli second */
#ifdef BCMDBG
#ifdef DEBUG
#define BRCMF_TRAP_INFO_SIZE 80
@ -84,7 +86,7 @@ struct rte_console {
char cbuf[CBUF_LEN];
};
#endif /* BCMDBG */
#endif /* DEBUG */
#include <chipcommon.h>
#include "dhd_bus.h"
@ -416,7 +418,7 @@ struct sdpcmd_regs {
u16 PAD[0x80];
};
#ifdef BCMDBG
#ifdef DEBUG
/* Device console log buffer state */
struct brcmf_console {
uint count; /* Poll interval msec counter */
@ -426,7 +428,7 @@ struct brcmf_console {
u8 *buf; /* Log buffer (host copy) */
uint last; /* Last buffer read index */
};
#endif /* BCMDBG */
#endif /* DEBUG */
struct sdpcm_shared {
u32 flags;
@ -507,11 +509,11 @@ struct brcmf_sdio {
uint polltick; /* Tick counter */
uint pollcnt; /* Count of active polls */
#ifdef BCMDBG
#ifdef DEBUG
uint console_interval;
struct brcmf_console console; /* Console output polling support */
uint console_addr; /* Console address from shared struct */
#endif /* BCMDBG */
#endif /* DEBUG */
uint regfails; /* Count of R_REG failures */
@ -587,10 +589,10 @@ struct brcmf_sdio {
#define CLK_PENDING 2 /* Not used yet */
#define CLK_AVAIL 3
#ifdef BCMDBG
#ifdef DEBUG
static int qcount[NUMPRIO];
static int tx_packets[NUMPRIO];
#endif /* BCMDBG */
#endif /* DEBUG */
#define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
@ -764,12 +766,12 @@ static int brcmf_sdbrcm_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
bus->clkstate = CLK_AVAIL;
brcmf_dbg(INFO, "CLKCTL: turned ON\n");
#if defined(BCMDBG)
#if defined(DEBUG)
if (bus->alp_only != true) {
if (SBSDIO_ALPONLY(clkctl))
brcmf_dbg(ERROR, "HT Clock should be on\n");
}
#endif /* defined (BCMDBG) */
#endif /* defined (DEBUG) */
bus->activity = true;
} else {
@ -814,9 +816,9 @@ static int brcmf_sdbrcm_sdclk(struct brcmf_sdio *bus, bool on)
/* Transition SD and backplane clock readiness */
static int brcmf_sdbrcm_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
{
#ifdef BCMDBG
#ifdef DEBUG
uint oldstate = bus->clkstate;
#endif /* BCMDBG */
#endif /* DEBUG */
brcmf_dbg(TRACE, "Enter\n");
@ -861,9 +863,9 @@ static int brcmf_sdbrcm_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
brcmf_sdbrcm_wd_timer(bus, 0);
break;
}
#ifdef BCMDBG
#ifdef DEBUG
brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
#endif /* BCMDBG */
#endif /* DEBUG */
return 0;
}
@ -1279,13 +1281,10 @@ static u8 brcmf_sdbrcm_rxglom(struct brcmf_sdio *bus, u8 rxseq)
}
return 0;
}
#ifdef BCMDBG
if (BRCMF_GLOM_ON()) {
printk(KERN_DEBUG "SUPERFRAME:\n");
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
pfirst->data, min_t(int, pfirst->len, 48));
}
#endif
brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
pfirst->data, min_t(int, pfirst->len, 48),
"SUPERFRAME:\n");
/* Validate the superframe header */
dptr = (u8 *) (pfirst->data);
@ -1362,13 +1361,8 @@ static u8 brcmf_sdbrcm_rxglom(struct brcmf_sdio *bus, u8 rxseq)
check = get_unaligned_le16(dptr + sizeof(u16));
chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
#ifdef BCMDBG
if (BRCMF_GLOM_ON()) {
printk(KERN_DEBUG "subframe:\n");
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
dptr, 32);
}
#endif
brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
dptr, 32, "subframe:\n");
if ((u16)~(sublen ^ check)) {
brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
@ -1433,13 +1427,8 @@ static u8 brcmf_sdbrcm_rxglom(struct brcmf_sdio *bus, u8 rxseq)
}
rxseq++;
#ifdef BCMDBG
if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
printk(KERN_DEBUG "Rx Subframe Data:\n");
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
dptr, dlen);
}
#endif
brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
dptr, dlen, "Rx Subframe Data:\n");
__skb_trim(pfirst, sublen);
skb_pull(pfirst, doff);
@ -1457,17 +1446,13 @@ static u8 brcmf_sdbrcm_rxglom(struct brcmf_sdio *bus, u8 rxseq)
continue;
}
#ifdef BCMDBG
if (BRCMF_GLOM_ON()) {
brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
bus->glom.qlen, pfirst, pfirst->data,
pfirst->len, pfirst->next,
pfirst->prev);
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
pfirst->data,
min_t(int, pfirst->len, 32));
}
#endif /* BCMDBG */
brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
pfirst->data,
min_t(int, pfirst->len, 32),
"subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
bus->glom.qlen, pfirst, pfirst->data,
pfirst->len, pfirst->next,
pfirst->prev);
}
/* sent any remaining packets up */
if (bus->glom.qlen) {
@ -1584,12 +1569,8 @@ brcmf_sdbrcm_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
gotpkt:
#ifdef BCMDBG
if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
printk(KERN_DEBUG "RxCtrl:\n");
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
}
#endif
brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
bus->rxctl, len, "RxCtrl:\n");
/* Point to valid data and indicate its length */
bus->rxctl += doff;
@ -1818,17 +1799,13 @@ brcmf_sdbrcm_readframes(struct brcmf_sdio *bus, uint maxframes, bool *finished)
}
bus->tx_max = txmax;
#ifdef BCMDBG
if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
printk(KERN_DEBUG "Rx Data:\n");
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
rxbuf, len);
} else if (BRCMF_HDRS_ON()) {
printk(KERN_DEBUG "RxHdr:\n");
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
bus->rxhdr, SDPCM_HDRLEN);
}
#endif
brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
rxbuf, len, "Rx Data:\n");
brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
BRCMF_DATA_ON()) &&
BRCMF_HDRS_ON(),
bus->rxhdr, SDPCM_HDRLEN,
"RxHdr:\n");
if (chan == SDPCM_CONTROL_CHANNEL) {
brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
@ -1865,13 +1842,9 @@ brcmf_sdbrcm_readframes(struct brcmf_sdio *bus, uint maxframes, bool *finished)
brcmf_sdbrcm_rxfail(bus, true, true);
continue;
}
#ifdef BCMDBG
if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
printk(KERN_DEBUG "RxHdr:\n");
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
bus->rxhdr, SDPCM_HDRLEN);
}
#endif
brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
bus->rxhdr, SDPCM_HDRLEN, "RxHdr:\n");
/* Extract hardware header fields */
len = get_unaligned_le16(bus->rxhdr);
@ -2024,13 +1997,8 @@ brcmf_sdbrcm_readframes(struct brcmf_sdio *bus, uint maxframes, bool *finished)
skb_push(pkt, BRCMF_FIRSTREAD);
memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD);
#ifdef BCMDBG
if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
printk(KERN_DEBUG "Rx Data:\n");
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
pkt->data, len);
}
#endif
brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
pkt->data, len, "Rx Data:\n");
deliver:
/* Save superframe descriptor and allocate packet frame */
@ -2038,14 +2006,9 @@ deliver:
if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
len);
#ifdef BCMDBG
if (BRCMF_GLOM_ON()) {
printk(KERN_DEBUG "Glom Data:\n");
print_hex_dump_bytes("",
DUMP_PREFIX_OFFSET,
pkt->data, len);
}
#endif
brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
pkt->data, len,
"Glom Data:\n");
__skb_trim(pkt, len);
skb_pull(pkt, SDPCM_HDRLEN);
bus->glomd = pkt;
@ -2078,13 +2041,11 @@ deliver:
down(&bus->sdsem);
}
rxcount = maxframes - rxleft;
#ifdef BCMDBG
/* Message if we hit the limit */
if (!rxleft)
brcmf_dbg(DATA, "hit rx limit of %d frames\n",
maxframes);
else
#endif /* BCMDBG */
brcmf_dbg(DATA, "processed %d frames\n", rxcount);
/* Back off rxseq if awaiting rtx, update rx_seq */
if (bus->rxskip)
@ -2176,20 +2137,22 @@ static int brcmf_sdbrcm_txpkt(struct brcmf_sdio *bus, struct sk_buff *pkt,
put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
#ifdef BCMDBG
#ifdef DEBUG
tx_packets[pkt->priority]++;
if (BRCMF_BYTES_ON() &&
(((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
(BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
printk(KERN_DEBUG "Tx Frame:\n");
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
} else if (BRCMF_HDRS_ON()) {
printk(KERN_DEBUG "TxHdr:\n");
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
frame, min_t(u16, len, 16));
}
#endif
brcmf_dbg_hex_dump(BRCMF_BYTES_ON() &&
((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
(BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)),
frame, len, "Tx Frame:\n");
brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
((BRCMF_CTL_ON() &&
chan == SDPCM_CONTROL_CHANNEL) ||
(BRCMF_DATA_ON() &&
chan != SDPCM_CONTROL_CHANNEL))) &&
BRCMF_HDRS_ON(),
frame, min_t(u16, len, 16), "TxHdr:\n");
/* Raise len to next SDIO block to eliminate tail command */
if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
u16 pad = bus->blocksize - (len % bus->blocksize);
@ -2410,7 +2373,7 @@ static bool brcmf_sdbrcm_dpc(struct brcmf_sdio *bus)
int err;
u8 clkctl, devctl = 0;
#ifdef BCMDBG
#ifdef DEBUG
/* Check for inconsistent device control */
devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
SBSDIO_DEVICE_CTL, &err);
@ -2418,7 +2381,7 @@ static bool brcmf_sdbrcm_dpc(struct brcmf_sdio *bus)
brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
}
#endif /* BCMDBG */
#endif /* DEBUG */
/* Read CSR, if clock on switch to AVAIL, else ignore */
clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
@ -2701,7 +2664,7 @@ static int brcmf_sdbrcm_bus_txdata(struct device *dev, struct sk_buff *pkt)
brcmf_txflowcontrol(bus->sdiodev->dev, 0, ON);
}
#ifdef BCMDBG
#ifdef DEBUG
if (pktq_plen(&bus->txq, prec) > qcount[prec])
qcount[prec] = pktq_plen(&bus->txq, prec);
#endif
@ -2774,7 +2737,7 @@ xfer_done:
return bcmerror;
}
#ifdef BCMDBG
#ifdef DEBUG
#define CONSOLE_LINE_MAX 192
static int brcmf_sdbrcm_readconsole(struct brcmf_sdio *bus)
@ -2845,14 +2808,14 @@ static int brcmf_sdbrcm_readconsole(struct brcmf_sdio *bus)
if (line[n - 1] == '\r')
n--;
line[n] = 0;
printk(KERN_DEBUG "CONSOLE: %s\n", line);
pr_debug("CONSOLE: %s\n", line);
}
}
break2:
return 0;
}
#endif /* BCMDBG */
#endif /* DEBUG */
static int brcmf_tx_frame(struct brcmf_sdio *bus, u8 *frame, u16 len)
{
@ -2982,17 +2945,11 @@ brcmf_sdbrcm_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
}
if (ret == -1) {
#ifdef BCMDBG
if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
printk(KERN_DEBUG "Tx Frame:\n");
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
frame, len);
} else if (BRCMF_HDRS_ON()) {
printk(KERN_DEBUG "TxHdr:\n");
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
frame, min_t(u16, len, 16));
}
#endif
brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
frame, len, "Tx Frame:\n");
brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
BRCMF_HDRS_ON(),
frame, min_t(u16, len, 16), "TxHdr:\n");
do {
ret = brcmf_tx_frame(bus, frame, len);
@ -3096,9 +3053,9 @@ static int brcmf_sdbrcm_write_vars(struct brcmf_sdio *bus)
u8 *vbuffer;
u32 varsizew;
__le32 varsizew_le;
#ifdef BCMDBG
#ifdef DEBUG
char *nvram_ularray;
#endif /* BCMDBG */
#endif /* DEBUG */
/* Even if there are no vars are to be written, we still
need to set the ramsize. */
@ -3115,7 +3072,7 @@ static int brcmf_sdbrcm_write_vars(struct brcmf_sdio *bus)
/* Write the vars list */
bcmerror =
brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
#ifdef BCMDBG
#ifdef DEBUG
/* Verify NVRAM bytes */
brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
@ -3142,7 +3099,7 @@ static int brcmf_sdbrcm_write_vars(struct brcmf_sdio *bus)
brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
kfree(nvram_ularray);
#endif /* BCMDBG */
#endif /* DEBUG */
kfree(vbuffer);
}
@ -3569,9 +3526,9 @@ void brcmf_sdbrcm_isr(void *arg)
static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus)
{
#ifdef BCMDBG
#ifdef DEBUG
struct brcmf_bus *bus_if = dev_get_drvdata(bus->sdiodev->dev);
#endif /* BCMDBG */
#endif /* DEBUG */
brcmf_dbg(TIMER, "Enter\n");
@ -3616,7 +3573,7 @@ static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus)
/* Update interrupt tracking */
bus->lastintrs = bus->intrcount;
}
#ifdef BCMDBG
#ifdef DEBUG
/* Poll for console output periodically */
if (bus_if->state == BRCMF_BUS_DATA &&
bus->console_interval != 0) {
@ -3630,7 +3587,7 @@ static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus)
bus->console_interval = 0;
}
}
#endif /* BCMDBG */
#endif /* DEBUG */
/* On idle timeout clear activity flag and/or turn off clock */
if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
@ -3721,11 +3678,8 @@ brcmf_sdbrcm_probe_attach(struct brcmf_sdio *bus, u32 regsva)
if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE))
brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
#ifdef BCMDBG
printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
#endif /* BCMDBG */
pr_debug("F1 signature read @0x18000000=0x%4x\n",
brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
/*
* Force PLL off until brcmf_sdio_chip_attach()
@ -3944,8 +3898,7 @@ void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev)
bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
bus, "brcmf_watchdog");
if (IS_ERR(bus->watchdog_tsk)) {
printk(KERN_WARNING
"brcmf_watchdog thread failed to start\n");
pr_warn("brcmf_watchdog thread failed to start\n");
bus->watchdog_tsk = NULL;
}
/* Initialize DPC thread */
@ -3953,8 +3906,7 @@ void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev)
bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
bus, "brcmf_dpc");
if (IS_ERR(bus->dpc_tsk)) {
printk(KERN_WARNING
"brcmf_dpc thread failed to start\n");
pr_warn("brcmf_dpc thread failed to start\n");
bus->dpc_tsk = NULL;
}

View File

@ -15,6 +15,8 @@
*/
/* ***** SDIO interface chip backplane handle functions ***** */
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/mmc/card.h>

View File

@ -16,6 +16,8 @@
/* Toplevel file. Relies on dhd_linux.c to send commands to the dongle. */
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/if_arp.h>
#include <linux/sched.h>
@ -2783,7 +2785,7 @@ static struct wireless_dev *brcmf_alloc_wdev(s32 sizeof_iface,
wiphy_new(&wl_cfg80211_ops,
sizeof(struct brcmf_cfg80211_priv) + sizeof_iface);
if (!wdev->wiphy) {
WL_ERR("Couldn not allocate wiphy device\n");
WL_ERR("Could not allocate wiphy device\n");
err = -ENOMEM;
goto wiphy_new_out;
}
@ -2809,7 +2811,7 @@ static struct wireless_dev *brcmf_alloc_wdev(s32 sizeof_iface,
*/
err = wiphy_register(wdev->wiphy);
if (err < 0) {
WL_ERR("Couldn not register wiphy device (%d)\n", err);
WL_ERR("Could not register wiphy device (%d)\n", err);
goto wiphy_register_out;
}
return wdev;

View File

@ -32,63 +32,63 @@ struct brcmf_cfg80211_ibss;
#define WL_DBG_MASK ((WL_DBG_INFO | WL_DBG_ERR | WL_DBG_TRACE) | \
(WL_DBG_SCAN) | (WL_DBG_CONN))
#define WL_ERR(fmt, args...) \
#define WL_ERR(fmt, ...) \
do { \
if (brcmf_dbg_level & WL_DBG_ERR) { \
if (net_ratelimit()) { \
printk(KERN_ERR "ERROR @%s : " fmt, \
__func__, ##args); \
pr_err("ERROR @%s : " fmt, \
__func__, ##__VA_ARGS__); \
} \
} \
} while (0)
#if (defined BCMDBG)
#define WL_INFO(fmt, args...) \
#if (defined DEBUG)
#define WL_INFO(fmt, ...) \
do { \
if (brcmf_dbg_level & WL_DBG_INFO) { \
if (net_ratelimit()) { \
printk(KERN_ERR "INFO @%s : " fmt, \
__func__, ##args); \
pr_err("INFO @%s : " fmt, \
__func__, ##__VA_ARGS__); \
} \
} \
} while (0)
#define WL_TRACE(fmt, args...) \
#define WL_TRACE(fmt, ...) \
do { \
if (brcmf_dbg_level & WL_DBG_TRACE) { \
if (net_ratelimit()) { \
printk(KERN_ERR "TRACE @%s : " fmt, \
__func__, ##args); \
pr_err("TRACE @%s : " fmt, \
__func__, ##__VA_ARGS__); \
} \
} \
} while (0)
#define WL_SCAN(fmt, args...) \
#define WL_SCAN(fmt, ...) \
do { \
if (brcmf_dbg_level & WL_DBG_SCAN) { \
if (net_ratelimit()) { \
printk(KERN_ERR "SCAN @%s : " fmt, \
__func__, ##args); \
pr_err("SCAN @%s : " fmt, \
__func__, ##__VA_ARGS__); \
} \
} \
} while (0)
#define WL_CONN(fmt, args...) \
#define WL_CONN(fmt, ...) \
do { \
if (brcmf_dbg_level & WL_DBG_CONN) { \
if (net_ratelimit()) { \
printk(KERN_ERR "CONN @%s : " fmt, \
__func__, ##args); \
pr_err("CONN @%s : " fmt, \
__func__, ##__VA_ARGS__); \
} \
} \
} while (0)
#else /* (defined BCMDBG) */
#else /* (defined DEBUG) */
#define WL_INFO(fmt, args...)
#define WL_TRACE(fmt, args...)
#define WL_SCAN(fmt, args...)
#define WL_CONN(fmt, args...)
#endif /* (defined BCMDBG) */
#endif /* (defined DEBUG) */
#define WL_NUM_SCAN_MAX 1
#define WL_NUM_PMKIDS_MAX MAXPMKID /* will be used

View File

@ -326,11 +326,11 @@
#define PCI_FORCEHT(sih) (PCIE(sih) && (ai_get_chip_id(sih) == BCM4716_CHIP_ID))
#ifdef BCMDBG
#ifdef DEBUG
#define SI_MSG(fmt, ...) pr_debug(fmt, ##__VA_ARGS__)
#else
#define SI_MSG(fmt, ...) no_printk(fmt, ##__VA_ARGS__)
#endif /* BCMDBG */
#endif /* DEBUG */
#define GOODCOREADDR(x, b) \
(((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \

View File

@ -915,7 +915,7 @@ brcms_c_ampdu_dotxstatus_complete(struct ampdu_info *ampdu, struct scb *scb,
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(p);
struct wiphy *wiphy = wlc->wiphy;
#ifdef BCMDBG
#ifdef DEBUG
u8 hole[AMPDU_MAX_MPDU];
memset(hole, 0, sizeof(hole));
#endif

View File

@ -177,7 +177,7 @@
#define BCMEXTRAHDROOM 172
/* debug/trace */
#ifdef BCMDBG
#ifdef DEBUG
#define DMA_ERROR(fmt, ...) \
do { \
if (*di->msg_level & 1) \
@ -193,7 +193,7 @@ do { \
no_printk(fmt, ##__VA_ARGS__)
#define DMA_TRACE(fmt, ...) \
no_printk(fmt, ##__VA_ARGS__)
#endif /* BCMDBG */
#endif /* DEBUG */
#define DMA_NONE(fmt, ...) \
no_printk(fmt, ##__VA_ARGS__)
@ -968,7 +968,7 @@ int dma_rx(struct dma_pub *pub, struct sk_buff_head *skb_list)
pktcnt++;
}
#ifdef BCMDBG
#ifdef DEBUG
if (resid > 0) {
uint cur;
cur =
@ -979,7 +979,7 @@ int dma_rx(struct dma_pub *pub, struct sk_buff_head *skb_list)
DMA_ERROR("rxin %d rxout %d, hw_curr %d\n",
di->rxin, di->rxout, cur);
}
#endif /* BCMDBG */
#endif /* DEBUG */
if ((di->dma.dmactrlflags & DMA_CTRL_RXMULTI) == 0) {
DMA_ERROR("%s: bad frame length (%d)\n",

View File

@ -15,6 +15,7 @@
*/
#define __UNDEF_NO_VERSION__
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/etherdevice.h>
#include <linux/sched.h>
@ -96,10 +97,10 @@ static struct bcma_device_id brcms_coreid_table[] = {
};
MODULE_DEVICE_TABLE(bcma, brcms_coreid_table);
#ifdef BCMDBG
#ifdef DEBUG
static int msglevel = 0xdeadbeef;
module_param(msglevel, int, 0);
#endif /* BCMDBG */
#endif /* DEBUG */
static struct ieee80211_channel brcms_2ghz_chantable[] = {
CHAN2GHZ(1, 2412, IEEE80211_CHAN_NO_HT40MINUS),
@ -857,7 +858,7 @@ static void brcms_free(struct brcms_info *wl)
/* free timers */
for (t = wl->timers; t; t = next) {
next = t->next;
#ifdef BCMDBG
#ifdef DEBUG
kfree(t->name);
#endif
kfree(t);
@ -1121,8 +1122,7 @@ static int __devinit brcms_bcma_probe(struct bcma_device *pdev)
wl = brcms_attach(pdev);
if (!wl) {
pr_err("%s: %s: brcms_attach failed!\n", KBUILD_MODNAME,
__func__);
pr_err("%s: brcms_attach failed!\n", __func__);
return -ENODEV;
}
return 0;
@ -1177,13 +1177,13 @@ static int __init brcms_module_init(void)
{
int error = -ENODEV;
#ifdef BCMDBG
#ifdef DEBUG
if (msglevel != 0xdeadbeef)
brcm_msg_level = msglevel;
#endif /* BCMDBG */
#endif /* DEBUG */
error = bcma_driver_register(&brcms_bcma_driver);
printk(KERN_ERR "%s: register returned %d\n", __func__, error);
pr_err("%s: register returned %d\n", __func__, error);
if (!error)
return 0;
@ -1367,7 +1367,7 @@ struct brcms_timer *brcms_init_timer(struct brcms_info *wl,
t->next = wl->timers;
wl->timers = t;
#ifdef BCMDBG
#ifdef DEBUG
t->name = kmalloc(strlen(name) + 1, GFP_ATOMIC);
if (t->name)
strcpy(t->name, name);
@ -1386,7 +1386,7 @@ void brcms_add_timer(struct brcms_timer *t, uint ms, int periodic)
{
struct ieee80211_hw *hw = t->wl->pub->ieee_hw;
#ifdef BCMDBG
#ifdef DEBUG
if (t->set)
wiphy_err(hw->wiphy, "%s: Already set. Name: %s, per %d\n",
__func__, t->name, periodic);
@ -1431,7 +1431,7 @@ void brcms_free_timer(struct brcms_timer *t)
if (wl->timers == t) {
wl->timers = wl->timers->next;
#ifdef BCMDBG
#ifdef DEBUG
kfree(t->name);
#endif
kfree(t);
@ -1443,7 +1443,7 @@ void brcms_free_timer(struct brcms_timer *t)
while (tmp) {
if (tmp->next == t) {
tmp->next = t->next;
#ifdef BCMDBG
#ifdef DEBUG
kfree(t->name);
#endif
kfree(t);

View File

@ -40,7 +40,7 @@ struct brcms_timer {
bool periodic;
bool set; /* indicates if timer is active */
struct brcms_timer *next; /* for freeing on unload */
#ifdef BCMDBG
#ifdef DEBUG
char *name; /* Description of the timer */
#endif
};

View File

@ -14,6 +14,8 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/pci_ids.h>
#include <linux/if_ether.h>
#include <net/mac80211.h>
@ -293,11 +295,11 @@ const u8 prio2fifo[NUMPRIO] = {
/* debug/trace */
uint brcm_msg_level =
#if defined(BCMDBG)
#if defined(DEBUG)
LOG_ERROR_VAL;
#else
0;
#endif /* BCMDBG */
#endif /* DEBUG */
/* TX FIFO number to WME/802.1E Access Category */
static const u8 wme_fifo2ac[] = {
@ -342,14 +344,14 @@ static const u16 xmtfifo_sz[][NFIFO] = {
{9, 58, 22, 14, 14, 5},
};
#ifdef BCMDBG
#ifdef DEBUG
static const char * const fifo_names[] = {
"AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
#else
static const char fifo_names[6][0];
#endif
#ifdef BCMDBG
#ifdef DEBUG
/* pointer to most recently allocated wl/wlc */
static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
#endif
@ -3075,30 +3077,30 @@ static void brcms_c_statsupd(struct brcms_c_info *wlc)
{
int i;
struct macstat macstats;
#ifdef BCMDBG
#ifdef DEBUG
u16 delta;
u16 rxf0ovfl;
u16 txfunfl[NFIFO];
#endif /* BCMDBG */
#endif /* DEBUG */
/* if driver down, make no sense to update stats */
if (!wlc->pub->up)
return;
#ifdef BCMDBG
#ifdef DEBUG
/* save last rx fifo 0 overflow count */
rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
/* save last tx fifo underflow count */
for (i = 0; i < NFIFO; i++)
txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
#endif /* BCMDBG */
#endif /* DEBUG */
/* Read mac stats from contiguous shared memory */
brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
sizeof(struct macstat), OBJADDR_SHM_SEL);
#ifdef BCMDBG
#ifdef DEBUG
/* check for rx fifo 0 overflow */
delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
if (delta)
@ -3114,7 +3116,7 @@ static void brcms_c_statsupd(struct brcms_c_info *wlc)
wiphy_err(wlc->wiphy, "wl%d: %u tx fifo %d underflows!"
"\n", wlc->pub->unit, delta, i);
}
#endif /* BCMDBG */
#endif /* DEBUG */
/* merge counters from dma module */
for (i = 0; i < NFIFO; i++) {
@ -5765,62 +5767,49 @@ int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
return -ENODATA;
}
#ifdef BCMDBG
static const char * const supr_reason[] = {
"None", "PMQ Entry", "Flush request",
"Previous frag failure", "Channel mismatch",
"Lifetime Expiry", "Underflow"
};
static void brcms_c_print_txs_status(u16 s)
{
printk(KERN_DEBUG "[15:12] %d frame attempts\n",
(s & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT);
printk(KERN_DEBUG " [11:8] %d rts attempts\n",
(s & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT);
printk(KERN_DEBUG " [7] %d PM mode indicated\n",
((s & TX_STATUS_PMINDCTD) ? 1 : 0));
printk(KERN_DEBUG " [6] %d intermediate status\n",
((s & TX_STATUS_INTERMEDIATE) ? 1 : 0));
printk(KERN_DEBUG " [5] %d AMPDU\n",
(s & TX_STATUS_AMPDU) ? 1 : 0);
printk(KERN_DEBUG " [4:2] %d Frame Suppressed Reason (%s)\n",
((s & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT),
supr_reason[(s & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT]);
printk(KERN_DEBUG " [1] %d acked\n",
((s & TX_STATUS_ACK_RCV) ? 1 : 0));
}
#endif /* BCMDBG */
void brcms_c_print_txstatus(struct tx_status *txs)
{
#if defined(BCMDBG)
u16 s = txs->status;
u16 ackphyrxsh = txs->ackphyrxsh;
pr_debug("\ntxpkt (MPDU) Complete\n");
printk(KERN_DEBUG "\ntxpkt (MPDU) Complete\n");
pr_debug("FrameID: %04x TxStatus: %04x\n", txs->frameid, txs->status);
printk(KERN_DEBUG "FrameID: %04x ", txs->frameid);
printk(KERN_DEBUG "TxStatus: %04x", s);
printk(KERN_DEBUG "\n");
pr_debug("[15:12] %d frame attempts\n",
(txs->status & TX_STATUS_FRM_RTX_MASK) >>
TX_STATUS_FRM_RTX_SHIFT);
pr_debug(" [11:8] %d rts attempts\n",
(txs->status & TX_STATUS_RTS_RTX_MASK) >>
TX_STATUS_RTS_RTX_SHIFT);
pr_debug(" [7] %d PM mode indicated\n",
txs->status & TX_STATUS_PMINDCTD ? 1 : 0);
pr_debug(" [6] %d intermediate status\n",
txs->status & TX_STATUS_INTERMEDIATE ? 1 : 0);
pr_debug(" [5] %d AMPDU\n",
txs->status & TX_STATUS_AMPDU ? 1 : 0);
pr_debug(" [4:2] %d Frame Suppressed Reason (%s)\n",
(txs->status & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT,
(const char *[]) {
"None",
"PMQ Entry",
"Flush request",
"Previous frag failure",
"Channel mismatch",
"Lifetime Expiry",
"Underflow"
} [(txs->status & TX_STATUS_SUPR_MASK) >>
TX_STATUS_SUPR_SHIFT]);
pr_debug(" [1] %d acked\n",
txs->status & TX_STATUS_ACK_RCV ? 1 : 0);
brcms_c_print_txs_status(s);
printk(KERN_DEBUG "LastTxTime: %04x ", txs->lasttxtime);
printk(KERN_DEBUG "Seq: %04x ", txs->sequence);
printk(KERN_DEBUG "PHYTxStatus: %04x ", txs->phyerr);
printk(KERN_DEBUG "RxAckRSSI: %04x ",
(ackphyrxsh & PRXS1_JSSI_MASK) >> PRXS1_JSSI_SHIFT);
printk(KERN_DEBUG "RxAckSQ: %04x",
(ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT);
printk(KERN_DEBUG "\n");
#endif /* defined(BCMDBG) */
pr_debug("LastTxTime: %04x Seq: %04x PHYTxStatus: %04x RxAckRSSI: %04x RxAckSQ: %04x\n",
txs->lasttxtime, txs->sequence, txs->phyerr,
(txs->ackphyrxsh & PRXS1_JSSI_MASK) >> PRXS1_JSSI_SHIFT,
(txs->ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT);
}
bool brcms_c_chipmatch(u16 vendor, u16 device)
{
if (vendor != PCI_VENDOR_ID_BROADCOM) {
pr_err("chipmatch: unknown vendor id %04x\n", vendor);
pr_err("unknown vendor id %04x\n", vendor);
return false;
}
@ -5833,11 +5822,11 @@ bool brcms_c_chipmatch(u16 vendor, u16 device)
if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
return true;
pr_err("chipmatch: unknown device id %04x\n", device);
pr_err("unknown device id %04x\n", device);
return false;
}
#if defined(BCMDBG)
#if defined(DEBUG)
void brcms_c_print_txdesc(struct d11txh *txh)
{
u16 mtcl = le16_to_cpu(txh->MacTxControlLow);
@ -5871,57 +5860,56 @@ void brcms_c_print_txdesc(struct d11txh *txh)
struct ieee80211_rts rts = txh->rts_frame;
/* add plcp header along with txh descriptor */
printk(KERN_DEBUG "Raw TxDesc + plcp header:\n");
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
txh, sizeof(struct d11txh) + 48);
brcmu_dbg_hex_dump(txh, sizeof(struct d11txh) + 48,
"Raw TxDesc + plcp header:\n");
printk(KERN_DEBUG "TxCtlLow: %04x ", mtcl);
printk(KERN_DEBUG "TxCtlHigh: %04x ", mtch);
printk(KERN_DEBUG "FC: %04x ", mfc);
printk(KERN_DEBUG "FES Time: %04x\n", tfest);
printk(KERN_DEBUG "PhyCtl: %04x%s ", ptcw,
pr_debug("TxCtlLow: %04x ", mtcl);
pr_debug("TxCtlHigh: %04x ", mtch);
pr_debug("FC: %04x ", mfc);
pr_debug("FES Time: %04x\n", tfest);
pr_debug("PhyCtl: %04x%s ", ptcw,
(ptcw & PHY_TXC_SHORT_HDR) ? " short" : "");
printk(KERN_DEBUG "PhyCtl_1: %04x ", ptcw_1);
printk(KERN_DEBUG "PhyCtl_1_Fbr: %04x\n", ptcw_1_Fbr);
printk(KERN_DEBUG "PhyCtl_1_Rts: %04x ", ptcw_1_Rts);
printk(KERN_DEBUG "PhyCtl_1_Fbr_Rts: %04x\n", ptcw_1_FbrRts);
printk(KERN_DEBUG "MainRates: %04x ", mainrates);
printk(KERN_DEBUG "XtraFrameTypes: %04x ", xtraft);
printk(KERN_DEBUG "\n");
pr_debug("PhyCtl_1: %04x ", ptcw_1);
pr_debug("PhyCtl_1_Fbr: %04x\n", ptcw_1_Fbr);
pr_debug("PhyCtl_1_Rts: %04x ", ptcw_1_Rts);
pr_debug("PhyCtl_1_Fbr_Rts: %04x\n", ptcw_1_FbrRts);
pr_debug("MainRates: %04x ", mainrates);
pr_debug("XtraFrameTypes: %04x ", xtraft);
pr_debug("\n");
print_hex_dump_bytes("SecIV:", DUMP_PREFIX_OFFSET, iv, sizeof(txh->IV));
print_hex_dump_bytes("RA:", DUMP_PREFIX_OFFSET,
ra, sizeof(txh->TxFrameRA));
printk(KERN_DEBUG "Fb FES Time: %04x ", tfestfb);
pr_debug("Fb FES Time: %04x ", tfestfb);
print_hex_dump_bytes("Fb RTS PLCP:", DUMP_PREFIX_OFFSET,
rtspfb, sizeof(txh->RTSPLCPFallback));
printk(KERN_DEBUG "RTS DUR: %04x ", rtsdfb);
pr_debug("RTS DUR: %04x ", rtsdfb);
print_hex_dump_bytes("PLCP:", DUMP_PREFIX_OFFSET,
fragpfb, sizeof(txh->FragPLCPFallback));
printk(KERN_DEBUG "DUR: %04x", fragdfb);
printk(KERN_DEBUG "\n");
pr_debug("DUR: %04x", fragdfb);
pr_debug("\n");
printk(KERN_DEBUG "MModeLen: %04x ", mmodelen);
printk(KERN_DEBUG "MModeFbrLen: %04x\n", mmodefbrlen);
pr_debug("MModeLen: %04x ", mmodelen);
pr_debug("MModeFbrLen: %04x\n", mmodefbrlen);
printk(KERN_DEBUG "FrameID: %04x\n", tfid);
printk(KERN_DEBUG "TxStatus: %04x\n", txs);
pr_debug("FrameID: %04x\n", tfid);
pr_debug("TxStatus: %04x\n", txs);
printk(KERN_DEBUG "MaxNumMpdu: %04x\n", mnmpdu);
printk(KERN_DEBUG "MaxAggbyte: %04x\n", mabyte);
printk(KERN_DEBUG "MaxAggbyte_fb: %04x\n", mabyte_f);
printk(KERN_DEBUG "MinByte: %04x\n", mmbyte);
pr_debug("MaxNumMpdu: %04x\n", mnmpdu);
pr_debug("MaxAggbyte: %04x\n", mabyte);
pr_debug("MaxAggbyte_fb: %04x\n", mabyte_f);
pr_debug("MinByte: %04x\n", mmbyte);
print_hex_dump_bytes("RTS PLCP:", DUMP_PREFIX_OFFSET,
rtsph, sizeof(txh->RTSPhyHeader));
print_hex_dump_bytes("RTS Frame:", DUMP_PREFIX_OFFSET,
(u8 *)&rts, sizeof(txh->rts_frame));
printk(KERN_DEBUG "\n");
pr_debug("\n");
}
#endif /* defined(BCMDBG) */
#endif /* defined(DEBUG) */
#if defined(BCMDBG)
#if defined(DEBUG)
static int
brcms_c_format_flags(const struct brcms_c_bit_desc *bd, u32 flags, char *buf,
int len)
@ -5975,9 +5963,9 @@ brcms_c_format_flags(const struct brcms_c_bit_desc *bd, u32 flags, char *buf,
return (int)(p - buf);
}
#endif /* defined(BCMDBG) */
#endif /* defined(DEBUG) */
#if defined(BCMDBG)
#if defined(DEBUG)
void brcms_c_print_rxh(struct d11rxhdr *rxh)
{
u16 len = rxh->RxFrameSize;
@ -5999,24 +5987,22 @@ void brcms_c_print_rxh(struct d11rxhdr *rxh)
{0, NULL}
};
printk(KERN_DEBUG "Raw RxDesc:\n");
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, rxh,
sizeof(struct d11rxhdr));
brcmu_dbg_hex_dump(rxh, sizeof(struct d11rxhdr), "Raw RxDesc:\n");
brcms_c_format_flags(macstat_flags, macstatus1, flagstr, 64);
snprintf(lenbuf, sizeof(lenbuf), "0x%x", len);
printk(KERN_DEBUG "RxFrameSize: %6s (%d)%s\n", lenbuf, len,
pr_debug("RxFrameSize: %6s (%d)%s\n", lenbuf, len,
(rxh->PhyRxStatus_0 & PRXS0_SHORTH) ? " short preamble" : "");
printk(KERN_DEBUG "RxPHYStatus: %04x %04x %04x %04x\n",
pr_debug("RxPHYStatus: %04x %04x %04x %04x\n",
phystatus_0, phystatus_1, phystatus_2, phystatus_3);
printk(KERN_DEBUG "RxMACStatus: %x %s\n", macstatus1, flagstr);
printk(KERN_DEBUG "RXMACaggtype: %x\n",
pr_debug("RxMACStatus: %x %s\n", macstatus1, flagstr);
pr_debug("RXMACaggtype: %x\n",
(macstatus2 & RXS_AGGTYPE_MASK));
printk(KERN_DEBUG "RxTSFTime: %04x\n", rxh->RxTSFTime);
pr_debug("RxTSFTime: %04x\n", rxh->RxTSFTime);
}
#endif /* defined(BCMDBG) */
#endif /* defined(DEBUG) */
u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
{
@ -8354,7 +8340,7 @@ brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
wlc->wiphy = wl->wiphy;
pub = wlc->pub;
#if defined(BCMDBG)
#if defined(DEBUG)
wlc_info_dbg = wlc;
#endif

View File

@ -648,10 +648,12 @@ extern void brcms_c_print_txstatus(struct tx_status *txs);
extern int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
uint *blocks);
#if defined(BCMDBG)
#if defined(DEBUG)
extern void brcms_c_print_txdesc(struct d11txh *txh);
#else
#define brcms_c_print_txdesc(a)
static inline void brcms_c_print_txdesc(struct d11txh *txh)
{
}
#endif
extern int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config);

View File

@ -14,6 +14,8 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/cordic.h>
@ -26434,8 +26436,7 @@ cal_try:
}
if (bcmerror != 0) {
printk(KERN_DEBUG "%s: Failed, cnt = %d\n", __func__,
cal_retry);
pr_debug("%s: Failed, cnt = %d\n", __func__, cal_retry);
if (cal_retry < CAL_RETRY_CNT) {
cal_retry++;

View File

@ -14,6 +14,8 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/netdevice.h>
#include <linux/module.h>
@ -240,17 +242,35 @@ struct sk_buff *brcmu_pktq_mdeq(struct pktq *pq, uint prec_bmp,
}
EXPORT_SYMBOL(brcmu_pktq_mdeq);
#if defined(BCMDBG)
#if defined(DEBUG)
/* pretty hex print a pkt buffer chain */
void brcmu_prpkt(const char *msg, struct sk_buff *p0)
{
struct sk_buff *p;
if (msg && (msg[0] != '\0'))
printk(KERN_DEBUG "%s:\n", msg);
pr_debug("%s:\n", msg);
for (p = p0; p; p = p->next)
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, p->data, p->len);
}
EXPORT_SYMBOL(brcmu_prpkt);
#endif /* defined(BCMDBG) */
void brcmu_dbg_hex_dump(const void *data, size_t size, const char *fmt, ...)
{
struct va_format vaf;
va_list args;
va_start(args, fmt);
vaf.fmt = fmt;
vaf.va = &args;
pr_debug("%pV", &vaf);
va_end(args);
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, data, size);
}
EXPORT_SYMBOL(brcmu_dbg_hex_dump);
#endif /* defined(DEBUG) */

View File

@ -176,10 +176,21 @@ struct ipv4_addr;
/* externs */
/* format/print */
#ifdef BCMDBG
#ifdef DEBUG
extern void brcmu_prpkt(const char *msg, struct sk_buff *p0);
#else
#define brcmu_prpkt(a, b)
#endif /* BCMDBG */
#endif /* DEBUG */
#ifdef DEBUG
extern __printf(3, 4)
void brcmu_dbg_hex_dump(const void *data, size_t size, const char *fmt, ...);
#else
__printf(3, 4)
static inline
void brcmu_dbg_hex_dump(const void *data, size_t size, const char *fmt, ...)
{
}
#endif
#endif /* _BRCMU_UTILS_H_ */

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portionhelp of the ieee80211 subsystem header files.
@ -1172,20 +1172,22 @@ int iwl_rx_dispatch(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb,
wake_up_all(&priv->shrd->notif_waitq);
}
if (priv->pre_rx_handler)
if (priv->pre_rx_handler &&
priv->shrd->ucode_owner == IWL_OWNERSHIP_TM)
priv->pre_rx_handler(priv, rxb);
/* Based on type of command response or notification,
* handle those that need handling via function in
* rx_handlers table. See iwl_setup_rx_handlers() */
if (priv->rx_handlers[pkt->hdr.cmd]) {
priv->rx_handlers_stats[pkt->hdr.cmd]++;
err = priv->rx_handlers[pkt->hdr.cmd] (priv, rxb, cmd);
} else {
/* No handling needed */
IWL_DEBUG_RX(priv,
"No handler needed for %s, 0x%02x\n",
get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
else {
/* Based on type of command response or notification,
* handle those that need handling via function in
* rx_handlers table. See iwl_setup_rx_handlers() */
if (priv->rx_handlers[pkt->hdr.cmd]) {
priv->rx_handlers_stats[pkt->hdr.cmd]++;
err = priv->rx_handlers[pkt->hdr.cmd] (priv, rxb, cmd);
} else {
/* No handling needed */
IWL_DEBUG_RX(priv,
"No handler needed for %s, 0x%02x\n",
get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
}
}
return err;
}

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.
@ -35,9 +35,12 @@
#include "iwl-trans.h"
/* priv->shrd->sta_lock must be held */
static void iwl_sta_ucode_activate(struct iwl_priv *priv, u8 sta_id)
static int iwl_sta_ucode_activate(struct iwl_priv *priv, u8 sta_id)
{
if (sta_id >= IWLAGN_STATION_COUNT) {
IWL_ERR(priv, "invalid sta_id %u", sta_id);
return -EINVAL;
}
if (!(priv->stations[sta_id].used & IWL_STA_DRIVER_ACTIVE))
IWL_ERR(priv, "ACTIVATE a non DRIVER active station id %u "
"addr %pM\n",
@ -53,6 +56,7 @@ static void iwl_sta_ucode_activate(struct iwl_priv *priv, u8 sta_id)
IWL_DEBUG_ASSOC(priv, "Added STA id %u addr %pM to uCode\n",
sta_id, priv->stations[sta_id].sta.sta.addr);
}
return 0;
}
static int iwl_process_add_sta_resp(struct iwl_priv *priv,
@ -77,8 +81,7 @@ static int iwl_process_add_sta_resp(struct iwl_priv *priv,
switch (pkt->u.add_sta.status) {
case ADD_STA_SUCCESS_MSK:
IWL_DEBUG_INFO(priv, "REPLY_ADD_STA PASSED\n");
iwl_sta_ucode_activate(priv, sta_id);
ret = 0;
ret = iwl_sta_ucode_activate(priv, sta_id);
break;
case ADD_STA_NO_ROOM_IN_TABLE:
IWL_ERR(priv, "Adding station %d failed, no room in table.\n",

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.
@ -315,7 +315,7 @@ static void iwl_bg_statistics_periodic(unsigned long data)
static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
u32 start_idx, u32 num_events,
u32 mode)
u32 capacity, u32 mode)
{
u32 i;
u32 ptr; /* SRAM byte address of log data */
@ -338,6 +338,15 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
iwl_write32(bus(priv), HBUS_TARG_MEM_RADDR, ptr);
rmb();
/*
* Refuse to read more than would have fit into the log from
* the current start_idx. This used to happen due to the race
* described below, but now WARN because the code below should
* prevent it from happening here.
*/
if (WARN_ON(num_events > capacity - start_idx))
num_events = capacity - start_idx;
/*
* "time" is actually "data" for mode 0 (no timestamp).
* place event id # at far right for easier visual parsing.
@ -346,12 +355,11 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
ev = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
time = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
if (mode == 0) {
trace_iwlwifi_dev_ucode_cont_event(priv,
0, time, ev);
trace_iwlwifi_dev_ucode_cont_event(priv, 0, time, ev);
} else {
data = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
trace_iwlwifi_dev_ucode_cont_event(priv,
time, data, ev);
trace_iwlwifi_dev_ucode_cont_event(priv, time,
data, ev);
}
}
/* Allow device to power down */
@ -362,53 +370,83 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
static void iwl_continuous_event_trace(struct iwl_priv *priv)
{
u32 capacity; /* event log capacity in # entries */
struct {
u32 capacity;
u32 mode;
u32 wrap_counter;
u32 write_counter;
} __packed read;
u32 base; /* SRAM byte address of event log header */
u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
u32 num_wraps; /* # times uCode wrapped to top of log */
u32 next_entry; /* index of next entry to be written by uCode */
base = priv->shrd->device_pointers.error_event_table;
base = priv->shrd->device_pointers.log_event_table;
if (iwlagn_hw_valid_rtc_data_addr(base)) {
capacity = iwl_read_targ_mem(bus(priv), base);
num_wraps = iwl_read_targ_mem(bus(priv),
base + (2 * sizeof(u32)));
mode = iwl_read_targ_mem(bus(priv), base + (1 * sizeof(u32)));
next_entry = iwl_read_targ_mem(bus(priv),
base + (3 * sizeof(u32)));
iwl_read_targ_mem_words(bus(priv), base, &read, sizeof(read));
capacity = read.capacity;
mode = read.mode;
num_wraps = read.wrap_counter;
next_entry = read.write_counter;
} else
return;
/*
* Unfortunately, the uCode doesn't use temporary variables.
* Therefore, it can happen that we read next_entry == capacity,
* which really means next_entry == 0.
*/
if (unlikely(next_entry == capacity))
next_entry = 0;
/*
* Additionally, the uCode increases the write pointer before
* the wraps counter, so if the write pointer is smaller than
* the old write pointer (wrap occurred) but we read that no
* wrap occurred, we actually read between the next_entry and
* num_wraps update (this does happen in practice!!) -- take
* that into account by increasing num_wraps.
*/
if (unlikely(next_entry < priv->event_log.next_entry &&
num_wraps == priv->event_log.num_wraps))
num_wraps++;
if (num_wraps == priv->event_log.num_wraps) {
iwl_print_cont_event_trace(priv,
base, priv->event_log.next_entry,
next_entry - priv->event_log.next_entry,
mode);
iwl_print_cont_event_trace(
priv, base, priv->event_log.next_entry,
next_entry - priv->event_log.next_entry,
capacity, mode);
priv->event_log.non_wraps_count++;
} else {
if ((num_wraps - priv->event_log.num_wraps) > 1)
if (num_wraps - priv->event_log.num_wraps > 1)
priv->event_log.wraps_more_count++;
else
priv->event_log.wraps_once_count++;
trace_iwlwifi_dev_ucode_wrap_event(priv,
num_wraps - priv->event_log.num_wraps,
next_entry, priv->event_log.next_entry);
if (next_entry < priv->event_log.next_entry) {
iwl_print_cont_event_trace(priv, base,
priv->event_log.next_entry,
capacity - priv->event_log.next_entry,
mode);
iwl_print_cont_event_trace(
priv, base, priv->event_log.next_entry,
capacity - priv->event_log.next_entry,
capacity, mode);
iwl_print_cont_event_trace(priv, base, 0,
next_entry, mode);
iwl_print_cont_event_trace(
priv, base, 0, next_entry, capacity, mode);
} else {
iwl_print_cont_event_trace(priv, base,
next_entry, capacity - next_entry,
mode);
iwl_print_cont_event_trace(
priv, base, next_entry,
capacity - next_entry,
capacity, mode);
iwl_print_cont_event_trace(priv, base, 0,
next_entry, mode);
iwl_print_cont_event_trace(
priv, base, 0, next_entry, capacity, mode);
}
}
priv->event_log.num_wraps = num_wraps;
priv->event_log.next_entry = next_entry;
}
@ -1219,6 +1257,11 @@ int iwl_alive_start(struct iwl_priv *priv)
if (iwl_is_rfkill(priv->shrd))
return -ERFKILL;
if (priv->event_log.ucode_trace) {
/* start collecting data now */
mod_timer(&priv->ucode_trace, jiffies);
}
/* download priority table before any calibration request */
if (cfg(priv)->bt_params &&
cfg(priv)->bt_params->advanced_bt_coexist) {
@ -2054,7 +2097,7 @@ MODULE_PARM_DESC(bt_coex_active, "enable wifi/bt co-exist (default: enable)");
module_param_named(led_mode, iwlagn_mod_params.led_mode, int, S_IRUGO);
MODULE_PARM_DESC(led_mode, "0=system default, "
"1=On(RF On)/Off(RF Off), 2=blinking (default: 0)");
"1=On(RF On)/Off(RF Off), 2=blinking, 3=Off (default: 0)");
module_param_named(power_save, iwlagn_mod_params.power_save,
bool, S_IRUGO);

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project.
*

View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -2131,9 +2131,10 @@ static ssize_t iwl_dbgfs_ucode_tracing_write(struct file *file,
if (trace) {
priv->event_log.ucode_trace = true;
/* schedule the ucode timer to occur in UCODE_TRACE_PERIOD */
mod_timer(&priv->ucode_trace,
jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
if (iwl_is_alive(priv->shrd)) {
/* start collecting data now */
mod_timer(&priv->ucode_trace, jiffies);
}
} else {
priv->event_log.ucode_trace = false;
del_timer_sync(&priv->ucode_trace);

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@ -661,7 +661,7 @@ struct traffic_stats {
* schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
* to perform continuous uCode event logging operation if enabled
*/
#define UCODE_TRACE_PERIOD (100)
#define UCODE_TRACE_PERIOD (10)
/*
* iwl_event_log: current uCode event log position

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2009 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2009 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2009 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2009 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project.
*

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project.
*

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@ -177,6 +177,10 @@ void iwl_leds_init(struct iwl_priv *priv)
int mode = iwlagn_mod_params.led_mode;
int ret;
if (mode == IWL_LED_DISABLE) {
IWL_INFO(priv, "Led disabled\n");
return;
}
if (mode == IWL_LED_DEFAULT)
mode = cfg(priv)->led_mode;

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -414,10 +414,25 @@ static u16 iwl_limit_dwell(struct iwl_priv *priv, u16 dwell_time)
for_each_context(priv, ctx) {
u16 value;
if (!iwl_is_associated_ctx(ctx))
continue;
if (ctx->staging.dev_type == RXON_DEV_TYPE_P2P)
switch (ctx->staging.dev_type) {
case RXON_DEV_TYPE_P2P:
/* no timing constraints */
continue;
case RXON_DEV_TYPE_ESS:
default:
/* timing constraints if associated */
if (!iwl_is_associated_ctx(ctx))
continue;
break;
case RXON_DEV_TYPE_CP:
case RXON_DEV_TYPE_2STA:
/*
* These seem to always have timers for TBTT
* active in uCode even when not associated yet.
*/
break;
}
value = ctx->beacon_int;
if (!value)
value = IWL_PASSIVE_DWELL_BASE;

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -102,7 +102,7 @@ struct iwl_trans_ops;
#define DRV_NAME "iwlwifi"
#define IWLWIFI_VERSION "in-tree:"
#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
#define DRV_COPYRIGHT "Copyright(c) 2003-2012 Intel Corporation"
#define DRV_AUTHOR "<ilw@linux.intel.com>"
extern struct iwl_mod_params iwlagn_mod_params;
@ -264,11 +264,13 @@ enum iwl_pa_type {
* LED ON = RF ON
* LED OFF = RF OFF
* IWL_LED_BLINK: adjust led blink rate based on blink table
* IWL_LED_DISABLE: led disabled
*/
enum iwl_led_mode {
IWL_LED_DEFAULT,
IWL_LED_RF_STATE,
IWL_LED_BLINK,
IWL_LED_DISABLE,
};
/**

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2010 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2010 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2010 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2010 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -115,6 +115,9 @@ struct nla_policy iwl_testmode_gnl_msg_policy[IWL_TM_ATTR_MAX] = {
[IWL_TM_ATTR_FW_VERSION] = { .type = NLA_U32, },
[IWL_TM_ATTR_DEVICE_ID] = { .type = NLA_U32, },
[IWL_TM_ATTR_FW_TYPE] = { .type = NLA_U32, },
[IWL_TM_ATTR_FW_INST_SIZE] = { .type = NLA_U32, },
[IWL_TM_ATTR_FW_DATA_SIZE] = { .type = NLA_U32, },
};
/*
@ -299,7 +302,7 @@ static int iwl_testmode_reg(struct ieee80211_hw *hw, struct nlattr **tb)
switch (nla_get_u32(tb[IWL_TM_ATTR_COMMAND])) {
case IWL_TM_CMD_APP2DEV_DIRECT_REG_READ32:
val32 = iwl_read32(bus(priv), ofs);
val32 = iwl_read_direct32(bus(priv), ofs);
IWL_INFO(priv, "32bit value to read 0x%x\n", val32);
skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, 20);
@ -321,7 +324,7 @@ static int iwl_testmode_reg(struct ieee80211_hw *hw, struct nlattr **tb)
} else {
val32 = nla_get_u32(tb[IWL_TM_ATTR_REG_VALUE32]);
IWL_INFO(priv, "32bit value to write 0x%x\n", val32);
iwl_write32(bus(priv), ofs, val32);
iwl_write_direct32(bus(priv), ofs, val32);
}
break;
case IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE8:
@ -422,7 +425,7 @@ static int iwl_testmode_driver(struct ieee80211_hw *hw, struct nlattr **tb)
struct sk_buff *skb;
unsigned char *rsp_data_ptr = NULL;
int status = 0, rsp_data_len = 0;
u32 devid;
u32 devid, inst_size = 0, data_size = 0;
switch (nla_get_u32(tb[IWL_TM_ATTR_COMMAND])) {
case IWL_TM_CMD_APP2DEV_GET_DEVICENAME:
@ -548,6 +551,41 @@ static int iwl_testmode_driver(struct ieee80211_hw *hw, struct nlattr **tb)
"Error sending msg : %d\n", status);
break;
case IWL_TM_CMD_APP2DEV_GET_FW_INFO:
skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, 20 + 8);
if (!skb) {
IWL_DEBUG_INFO(priv, "Error allocating memory\n");
return -ENOMEM;
}
switch (priv->shrd->ucode_type) {
case IWL_UCODE_REGULAR:
inst_size = trans(priv)->ucode_rt.code.len;
data_size = trans(priv)->ucode_rt.data.len;
break;
case IWL_UCODE_INIT:
inst_size = trans(priv)->ucode_init.code.len;
data_size = trans(priv)->ucode_init.data.len;
break;
case IWL_UCODE_WOWLAN:
inst_size = trans(priv)->ucode_wowlan.code.len;
data_size = trans(priv)->ucode_wowlan.data.len;
break;
case IWL_UCODE_NONE:
IWL_DEBUG_INFO(priv, "The uCode has not been loaded\n");
break;
default:
IWL_DEBUG_INFO(priv, "Unsupported uCode type\n");
break;
}
NLA_PUT_U32(skb, IWL_TM_ATTR_FW_TYPE, priv->shrd->ucode_type);
NLA_PUT_U32(skb, IWL_TM_ATTR_FW_INST_SIZE, inst_size);
NLA_PUT_U32(skb, IWL_TM_ATTR_FW_DATA_SIZE, data_size);
status = cfg80211_testmode_reply(skb);
if (status < 0)
IWL_DEBUG_INFO(priv,
"Error sending msg : %d\n", status);
break;
default:
IWL_DEBUG_INFO(priv, "Unknown testmode driver command ID\n");
return -ENOSYS;
@ -733,7 +771,7 @@ static int iwl_testmode_ownership(struct ieee80211_hw *hw, struct nlattr **tb)
static int iwl_testmode_sram(struct ieee80211_hw *hw, struct nlattr **tb)
{
struct iwl_priv *priv = hw->priv;
u32 base, ofs, size, maxsize;
u32 ofs, size, maxsize;
if (priv->testmode_sram.sram_readed)
return -EBUSY;
@ -759,25 +797,24 @@ static int iwl_testmode_sram(struct ieee80211_hw *hw, struct nlattr **tb)
maxsize = trans(priv)->ucode_wowlan.data.len;
break;
case IWL_UCODE_NONE:
IWL_DEBUG_INFO(priv, "Error, uCode does not been loaded\n");
IWL_ERR(priv, "Error, uCode does not been loaded\n");
return -ENOSYS;
default:
IWL_DEBUG_INFO(priv, "Error, unsupported uCode type\n");
IWL_ERR(priv, "Error, unsupported uCode type\n");
return -ENOSYS;
}
if ((ofs + size) > maxsize) {
IWL_DEBUG_INFO(priv, "Invalid offset/size: out of range\n");
if ((ofs + size) > (maxsize + SRAM_DATA_SEG_OFFSET)) {
IWL_ERR(priv, "Invalid offset/size: out of range\n");
return -EINVAL;
}
priv->testmode_sram.buff_size = (size / 4) * 4;
priv->testmode_sram.buff_addr =
kmalloc(priv->testmode_sram.buff_size, GFP_KERNEL);
if (priv->testmode_sram.buff_addr == NULL) {
IWL_DEBUG_INFO(priv, "Error allocating memory\n");
IWL_ERR(priv, "Error allocating memory\n");
return -ENOMEM;
}
base = 0x800000;
_iwl_read_targ_mem_words(bus(priv), base + ofs,
_iwl_read_targ_mem_words(bus(priv), ofs,
priv->testmode_sram.buff_addr,
priv->testmode_sram.buff_size / 4);
priv->testmode_sram.num_chunks =
@ -882,6 +919,7 @@ int iwlagn_mac_testmode_cmd(struct ieee80211_hw *hw, void *data, int len)
case IWL_TM_CMD_APP2DEV_LOAD_WOWLAN_FW:
case IWL_TM_CMD_APP2DEV_GET_FW_VERSION:
case IWL_TM_CMD_APP2DEV_GET_DEVICE_ID:
case IWL_TM_CMD_APP2DEV_GET_FW_INFO:
IWL_DEBUG_INFO(priv, "testmode cmd to driver\n");
result = iwl_testmode_driver(hw, tb);
break;

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2010 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2010 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2010 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2010 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -111,15 +111,17 @@
*
* @IWL_TM_CMD_APP2DEV_INDIRECT_REG_READ32:
* @IWL_TM_CMD_APP2DEV_INDIRECT_REG_WRITE32:
* commands from user applicaiton to indirectly access peripheral register
* commands from user application to indirectly access peripheral register
*
* @IWL_TM_CMD_APP2DEV_READ_SRAM:
* @IWL_TM_CMD_APP2DEV_DUMP_SRAM:
* commands from user applicaiton to read data in sram
* commands from user application to read data in sram
*
* @IWL_TM_CMD_APP2DEV_LOAD_WOWLAN_FW: load Weak On Wireless LAN uCode image
* @IWL_TM_CMD_APP2DEV_LOAD_WOWLAN_FW: load Wake On Wireless LAN uCode image
* @IWL_TM_CMD_APP2DEV_GET_FW_VERSION: retrieve uCode version
* @IWL_TM_CMD_APP2DEV_GET_DEVICE_ID: retrieve ID information in device
* @IWL_TM_CMD_APP2DEV_GET_FW_INFO:
* retrieve information of existing loaded uCode image
*
*/
enum iwl_tm_cmd_t {
@ -147,7 +149,8 @@ enum iwl_tm_cmd_t {
IWL_TM_CMD_APP2DEV_LOAD_WOWLAN_FW = 22,
IWL_TM_CMD_APP2DEV_GET_FW_VERSION = 23,
IWL_TM_CMD_APP2DEV_GET_DEVICE_ID = 24,
IWL_TM_CMD_MAX = 25,
IWL_TM_CMD_APP2DEV_GET_FW_INFO = 25,
IWL_TM_CMD_MAX = 26,
};
/*
@ -237,6 +240,15 @@ enum iwl_tm_cmd_t {
* When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_APP2DEV_GET_DEVICE_ID,
* IWL_TM_ATTR_DEVICE_ID for the device ID information
*
* @IWL_TM_ATTR_FW_TYPE:
* @IWL_TM_ATTR_FW_INST_SIZE:
* @IWL_TM_ATTR_FW_DATA_SIZE:
* When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_APP2DEV_GET_FW_INFO,
* The mandatory fields are:
* IWL_TM_ATTR_FW_TYPE for the uCode type (INIT/RUNTIME/...)
* IWL_TM_ATTR_FW_INST_SIZE for the size of instruction section
* IWL_TM_ATTR_FW_DATA_SIZE for the size of data section
*
*/
enum iwl_tm_attr_t {
IWL_TM_ATTR_NOT_APPLICABLE = 0,
@ -259,7 +271,10 @@ enum iwl_tm_attr_t {
IWL_TM_ATTR_SRAM_DUMP = 17,
IWL_TM_ATTR_FW_VERSION = 18,
IWL_TM_ATTR_DEVICE_ID = 19,
IWL_TM_ATTR_MAX = 20,
IWL_TM_ATTR_FW_TYPE = 20,
IWL_TM_ATTR_FW_INST_SIZE = 21,
IWL_TM_ATTR_FW_DATA_SIZE = 22,
IWL_TM_ATTR_MAX = 23,
};
/* uCode trace buffer */
@ -271,4 +286,7 @@ enum iwl_tm_attr_t {
/* Maximum data size of each dump it packet */
#define DUMP_CHUNK_SIZE (PAGE_SIZE - 1024)
/* Address offset of data segment in SRAM */
#define SRAM_DATA_SEG_OFFSET 0x800000
#endif

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as

View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -182,7 +182,8 @@ mwifiex_11n_aggregate_pkt(struct mwifiex_private *priv,
skb_reserve(skb_aggr, headroom + sizeof(struct txpd));
tx_info_aggr = MWIFIEX_SKB_TXCB(skb_aggr);
tx_info_aggr->bss_index = tx_info_src->bss_index;
tx_info_aggr->bss_type = tx_info_src->bss_type;
tx_info_aggr->bss_num = tx_info_src->bss_num;
skb_aggr->priority = skb_src->priority;
do {

View File

@ -79,7 +79,7 @@ static int
mwifiex_cfg80211_del_key(struct wiphy *wiphy, struct net_device *netdev,
u8 key_index, bool pairwise, const u8 *mac_addr)
{
struct mwifiex_private *priv = mwifiex_cfg80211_get_priv(wiphy);
struct mwifiex_private *priv = mwifiex_netdev_get_priv(netdev);
if (mwifiex_set_encode(priv, NULL, 0, key_index, 1)) {
wiphy_err(wiphy, "deleting the crypto keys\n");
@ -122,7 +122,7 @@ mwifiex_cfg80211_set_power_mgmt(struct wiphy *wiphy,
struct net_device *dev,
bool enabled, int timeout)
{
struct mwifiex_private *priv = mwifiex_cfg80211_get_priv(wiphy);
struct mwifiex_private *priv = mwifiex_netdev_get_priv(dev);
u32 ps_mode;
if (timeout)
@ -143,7 +143,7 @@ mwifiex_cfg80211_set_default_key(struct wiphy *wiphy, struct net_device *netdev,
u8 key_index, bool unicast,
bool multicast)
{
struct mwifiex_private *priv = mwifiex_cfg80211_get_priv(wiphy);
struct mwifiex_private *priv = mwifiex_netdev_get_priv(netdev);
/* Return if WEP key not configured */
if (priv->sec_info.wep_status == MWIFIEX_802_11_WEP_DISABLED)
@ -165,7 +165,7 @@ mwifiex_cfg80211_add_key(struct wiphy *wiphy, struct net_device *netdev,
u8 key_index, bool pairwise, const u8 *mac_addr,
struct key_params *params)
{
struct mwifiex_private *priv = mwifiex_cfg80211_get_priv(wiphy);
struct mwifiex_private *priv = mwifiex_netdev_get_priv(netdev);
if (mwifiex_set_encode(priv, params->key, params->key_len,
key_index, 0)) {
@ -376,7 +376,7 @@ mwifiex_cfg80211_set_channel(struct wiphy *wiphy, struct net_device *dev,
struct ieee80211_channel *chan,
enum nl80211_channel_type channel_type)
{
struct mwifiex_private *priv = mwifiex_cfg80211_get_priv(wiphy);
struct mwifiex_private *priv = mwifiex_netdev_get_priv(dev);
if (priv->media_connected) {
wiphy_err(wiphy, "This setting is valid only when station "
@ -557,6 +557,23 @@ mwifiex_dump_station_info(struct mwifiex_private *priv,
/* bit rate is in 500 kb/s units. Convert it to 100kb/s units */
sinfo->txrate.legacy = rate.rate * 5;
if (priv->bss_mode == NL80211_IFTYPE_STATION) {
sinfo->filled |= STATION_INFO_BSS_PARAM;
sinfo->bss_param.flags = 0;
if (priv->curr_bss_params.bss_descriptor.cap_info_bitmap &
WLAN_CAPABILITY_SHORT_PREAMBLE)
sinfo->bss_param.flags |=
BSS_PARAM_FLAGS_SHORT_PREAMBLE;
if (priv->curr_bss_params.bss_descriptor.cap_info_bitmap &
WLAN_CAPABILITY_SHORT_SLOT_TIME)
sinfo->bss_param.flags |=
BSS_PARAM_FLAGS_SHORT_SLOT_TIME;
sinfo->bss_param.dtim_period =
priv->curr_bss_params.bss_descriptor.dtim_period;
sinfo->bss_param.beacon_interval =
priv->curr_bss_params.bss_descriptor.beacon_period;
}
return ret;
}
@ -1004,7 +1021,7 @@ static int
mwifiex_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev,
struct cfg80211_ibss_params *params)
{
struct mwifiex_private *priv = mwifiex_cfg80211_get_priv(wiphy);
struct mwifiex_private *priv = mwifiex_netdev_get_priv(dev);
int ret = 0;
if (priv->bss_mode != NL80211_IFTYPE_ADHOC) {
@ -1042,7 +1059,7 @@ done:
static int
mwifiex_cfg80211_leave_ibss(struct wiphy *wiphy, struct net_device *dev)
{
struct mwifiex_private *priv = mwifiex_cfg80211_get_priv(wiphy);
struct mwifiex_private *priv = mwifiex_netdev_get_priv(dev);
wiphy_dbg(wiphy, "info: disconnecting from essid %pM\n",
priv->cfg_bssid);
@ -1217,7 +1234,6 @@ struct net_device *mwifiex_add_virtual_intf(struct wiphy *wiphy,
priv->frame_type = MWIFIEX_DATA_FRAME_TYPE_ETH_II;
priv->bss_priority = 0;
priv->bss_role = MWIFIEX_BSS_ROLE_STA;
priv->bss_index = 0;
priv->bss_num = 0;
break;
@ -1281,10 +1297,7 @@ EXPORT_SYMBOL_GPL(mwifiex_add_virtual_intf);
*/
int mwifiex_del_virtual_intf(struct wiphy *wiphy, struct net_device *dev)
{
struct mwifiex_private *priv = mwifiex_cfg80211_get_priv(wiphy);
if (!priv || !dev)
return 0;
struct mwifiex_private *priv = mwifiex_netdev_get_priv(dev);
#ifdef CONFIG_DEBUG_FS
mwifiex_dev_debugfs_remove(priv);

View File

@ -391,7 +391,8 @@ int mwifiex_process_event(struct mwifiex_adapter *adapter)
if (skb) {
rx_info = MWIFIEX_SKB_RXCB(skb);
rx_info->bss_index = priv->bss_index;
rx_info->bss_num = priv->bss_num;
rx_info->bss_type = priv->bss_type;
}
if (eventcause != EVENT_PS_SLEEP && eventcause != EVENT_PS_AWAKE) {

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