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clk: tegra: Add missing Tegra210 clocks

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iqc1, iqc2, tegra_clk_pll_a_out_adsp, tegra_clk_pll_a_out0_out_adsp, adsp
and adsp neon were not modelled. dp2 wasn't modelled for Tegra210.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Peter De Schrijver 2017-03-22 16:23:16 +02:00 committed by Thierry Reding
parent a63b6186f9
commit 88da44c5ed
4 changed files with 27 additions and 8 deletions
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6
drivers/clk/tegra/clk-id.h
View File

@ -318,6 +318,12 @@ enum clk_id {
tegra_clk_dmic1_sync_clk_mux,
tegra_clk_dmic2_sync_clk_mux,
tegra_clk_dmic3_sync_clk_mux,
tegra_clk_iqc1,
tegra_clk_iqc2,
tegra_clk_pll_a_out_adsp,
tegra_clk_pll_a_out0_out_adsp,
tegra_clk_adsp,
tegra_clk_adsp_neon,
tegra_clk_max,
};

6
drivers/clk/tegra/clk-tegra-periph.c
View File

@ -859,6 +859,12 @@ static struct tegra_periph_init_data gate_clks[] = {
GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0),
GATE("cec", "pclk", 136, 0, tegra_clk_cec, 0),
GATE("iqc1", "clk_m", 221, 0, tegra_clk_iqc1, 0),
GATE("iqc2", "clk_m", 220, 0, tegra_clk_iqc1, 0),
GATE("pll_a_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out_adsp, 0),
GATE("pll_a_out0_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out0_out_adsp, 0),
GATE("adsp", "aclk", 199, 0, tegra_clk_adsp, 0),
GATE("adsp_neon", "aclk", 218, 0, tegra_clk_adsp_neon, 0),
};
static struct tegra_periph_init_data div_clks[] = {

7
drivers/clk/tegra/clk-tegra210.c
View File

@ -2326,6 +2326,13 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
[tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true },
[tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true },
[tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true },
[tegra_clk_dp2] = { .dt_id = TEGRA210_CLK_DP2, .present = true },
[tegra_clk_iqc1] = { .dt_id = TEGRA210_CLK_IQC1, .present = true },
[tegra_clk_iqc2] = { .dt_id = TEGRA210_CLK_IQC2, .present = true },
[tegra_clk_pll_a_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT_ADSP, .present = true },
[tegra_clk_pll_a_out0_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP, .present = true },
[tegra_clk_adsp] = { .dt_id = TEGRA210_CLK_ADSP, .present = true },
[tegra_clk_adsp_neon] = { .dt_id = TEGRA210_CLK_ADSP_NEON, .present = true },
};
static struct tegra_devclk devclks[] __initdata = {

16
include/dt-bindings/clock/tegra210-car.h
View File

@ -173,7 +173,7 @@
#define TEGRA210_CLK_ENTROPY 149
/* 150 */
/* 151 */
/* 152 */
#define TEGRA210_CLK_DP2 152
/* 153 */
/* 154 */
/* 155 (bit affects dfll_ref and dfll_soc) */
@ -210,7 +210,7 @@
#define TEGRA210_CLK_DBGAPB 185
/* 186 */
#define TEGRA210_CLK_PLL_P_OUT_ADSP 187
/* 188 */
/* 188 ((bit affects pll_a_out_adsp and pll_a_out0_out_adsp)*/
#define TEGRA210_CLK_PLL_G_REF 189
/* 190 */
/* 191 */
@ -222,7 +222,7 @@
/* 196 */
#define TEGRA210_CLK_DMIC3 197
#define TEGRA210_CLK_APE 198
/* 199 */
#define TEGRA210_CLK_ADSP 199
/* 200 */
/* 201 */
#define TEGRA210_CLK_MAUD 202
@ -241,10 +241,10 @@
/* 215 */
/* 216 */
/* 217 */
/* 218 */
#define TEGRA210_CLK_ADSP_NEON 218
#define TEGRA210_CLK_NVENC 219
/* 220 */
/* 221 */
#define TEGRA210_CLK_IQC2 220
#define TEGRA210_CLK_IQC1 221
#define TEGRA210_CLK_SOR_SAFE 222
#define TEGRA210_CLK_PLL_P_OUT_CPU 223
@ -350,8 +350,8 @@
/* 320 */
/* 321 */
#define TEGRA210_CLK_ISP 322
/* 323 */
/* 324 */
#define TEGRA210_CLK_PLL_A_OUT_ADSP 323
#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
/* 325 */
/* 326 */
/* 327 */