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net: ethernet: mtk_eth_soc: drop clocks unused by Ethernet driver

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Clocks for SerDes and PHY are going to be handled by standalone drivers
for each of those hardware components. Drop them from the Ethernet driver.

The clocks which are being removed for this patch are responsible for
the for the SerDes PCS and PHYs used for the 2nd and 3rd MAC which are
anyway not yet supported. Hence backwards compatibility is not an issue.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/b5faaf69b5c6e3e155c64af03706c3c423c6a1c9.1722335682.git.daniel@makrotopia.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Daniel Golle 2024-07-30 11:36:42 +01:00 committed by Jakub Kicinski
parent 501c3005f0
commit 887b1d1adb
1 changed files with 0 additions and 14 deletions
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14
drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@ -724,12 +724,8 @@ enum mtk_clks_map {
MTK_CLK_ETHWARP_WOCPU2,
MTK_CLK_ETHWARP_WOCPU1,
MTK_CLK_ETHWARP_WOCPU0,
MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
MTK_CLK_TOP_SGM_0_SEL,
MTK_CLK_TOP_SGM_1_SEL,
MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
MTK_CLK_TOP_ETH_GMII_SEL,
MTK_CLK_TOP_ETH_REFCK_50M_SEL,
MTK_CLK_TOP_ETH_SYS_200M_SEL,
@ -800,19 +796,9 @@ enum mtk_clks_map {
BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
BIT_ULL(MTK_CLK_CRYPTO) | \
BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \