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Merge branch 'x86/apic' into x86/core

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This commit is contained in:
Ingo Molnar 2008-08-14 15:13:47 +02:00
commit 881b374705
6 changed files with 61 additions and 35 deletions
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16
arch/x86/kernel/apic_32.c
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@ -205,11 +205,15 @@ EXPORT_SYMBOL_GPL(apic_ops);
*/
void __cpuinit enable_NMI_through_LVT0(void)
{
unsigned int v = APIC_DM_NMI;
unsigned int v;
/* Level triggered for 82489DX */
/* unmask and set to NMI */
v = APIC_DM_NMI;
/* Level triggered for 82489DX (32bit mode) */
if (!lapic_is_integrated())
v |= APIC_LVT_LEVEL_TRIGGER;
apic_write(APIC_LVT0, v);
}
@ -226,9 +230,13 @@ int get_physical_broadcast(void)
*/
int lapic_get_maxlvt(void)
{
unsigned int v = apic_read(APIC_LVR);
unsigned int v;
/* 82489DXs do not report # of LVT entries. */
v = apic_read(APIC_LVR);
/*
* - we always have APIC integrated on 64bit mode
* - 82489DXs do not report # of LVT entries
*/
return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
}

14
arch/x86/kernel/apic_64.c
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@ -220,6 +220,11 @@ void __cpuinit enable_NMI_through_LVT0(void)
/* unmask and set to NMI */
v = APIC_DM_NMI;
/* Level triggered for 82489DX (32bit mode) */
if (!lapic_is_integrated())
v |= APIC_LVT_LEVEL_TRIGGER;
apic_write(APIC_LVT0, v);
}
@ -228,11 +233,14 @@ void __cpuinit enable_NMI_through_LVT0(void)
*/
int lapic_get_maxlvt(void)
{
unsigned int v, maxlvt;
unsigned int v;
v = apic_read(APIC_LVR);
maxlvt = GET_APIC_MAXLVT(v);
return maxlvt;
/*
* - we always have APIC integrated on 64bit mode
* - 82489DXs do not report # of LVT entries
*/
return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
}
/*

29
arch/x86/kernel/io_apic_32.c
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@ -51,6 +51,8 @@
#include <mach_apic.h>
#include <mach_apicdef.h>
#define __apicdebuginit(type) static type __init
int (*ioapic_renumber_irq)(int ioapic, int irq);
atomic_t irq_mis_count;
@ -1342,7 +1344,8 @@ static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
ioapic_write_entry(apic, pin, entry);
}
void __init print_IO_APIC(void)
__apicdebuginit(void) print_IO_APIC(void)
{
int apic, i;
union IO_APIC_reg_00 reg_00;
@ -1457,9 +1460,7 @@ void __init print_IO_APIC(void)
return;
}
#if 0
static void print_APIC_bitfield(int base)
__apicdebuginit(void) print_APIC_bitfield(int base)
{
unsigned int v;
int i, j;
@ -1480,7 +1481,7 @@ static void print_APIC_bitfield(int base)
}
}
void /*__init*/ print_local_APIC(void *dummy)
__apicdebuginit(void) print_local_APIC(void *dummy)
{
unsigned int v, ver, maxlvt;
u64 icr;
@ -1564,12 +1565,12 @@ void /*__init*/ print_local_APIC(void *dummy)
printk("\n");
}
void print_all_local_APICs(void)
__apicdebuginit(void) print_all_local_APICs(void)
{
on_each_cpu(print_local_APIC, NULL, 1);
}
void /*__init*/ print_PIC(void)
__apicdebuginit(void) print_PIC(void)
{
unsigned int v;
unsigned long flags;
@ -1601,7 +1602,17 @@ void /*__init*/ print_PIC(void)
printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
}
#endif /* 0 */
__apicdebuginit(int) print_all_ICs(void)
{
print_PIC();
print_all_local_APICs();
print_IO_APIC();
return 0;
}
fs_initcall(print_all_ICs);
static void __init enable_IO_APIC(void)
{
@ -2327,8 +2338,6 @@ void __init setup_IO_APIC(void)
setup_IO_APIC_irqs();
init_IO_APIC_traps();
check_timer();
if (!acpi_ioapic)
print_IO_APIC();
}
/*

31
arch/x86/kernel/io_apic_64.c
View File

@ -55,6 +55,8 @@
#include <mach_ipi.h>
#include <mach_apic.h>
#define __apicdebuginit(type) static type __init
struct irq_cfg {
cpumask_t domain;
cpumask_t old_domain;
@ -89,8 +91,6 @@ int first_system_vector = 0xfe;
char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
#define __apicdebuginit __init
int sis_apic_bug; /* not actually supported, dummy for compile */
static int no_timer_check;
@ -1117,7 +1117,8 @@ static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
ioapic_write_entry(apic, pin, entry);
}
void __apicdebuginit print_IO_APIC(void)
__apicdebuginit(void) print_IO_APIC(void)
{
int apic, i;
union IO_APIC_reg_00 reg_00;
@ -1211,9 +1212,7 @@ void __apicdebuginit print_IO_APIC(void)
return;
}
#if 0
static __apicdebuginit void print_APIC_bitfield (int base)
__apicdebuginit(void) print_APIC_bitfield(int base)
{
unsigned int v;
int i, j;
@ -1234,7 +1233,7 @@ static __apicdebuginit void print_APIC_bitfield (int base)
}
}
void __apicdebuginit print_local_APIC(void * dummy)
__apicdebuginit(void) print_local_APIC(void *dummy)
{
unsigned int v, ver, maxlvt;
unsigned long icr;
@ -1311,12 +1310,12 @@ void __apicdebuginit print_local_APIC(void * dummy)
printk("\n");
}
void print_all_local_APICs (void)
__apicdebuginit(void) print_all_local_APICs(void)
{
on_each_cpu(print_local_APIC, NULL, 1);
}
void __apicdebuginit print_PIC(void)
__apicdebuginit(void) print_PIC(void)
{
unsigned int v;
unsigned long flags;
@ -1348,7 +1347,17 @@ void __apicdebuginit print_PIC(void)
printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
}
#endif /* 0 */
__apicdebuginit(int) print_all_ICs(void)
{
print_PIC();
print_all_local_APICs();
print_IO_APIC();
return 0;
}
fs_initcall(print_all_ICs);
void __init enable_IO_APIC(void)
{
@ -2172,8 +2181,6 @@ void __init setup_IO_APIC(void)
setup_IO_APIC_irqs();
init_IO_APIC_traps();
check_timer();
if (!acpi_ioapic)
print_IO_APIC();
}
struct sysfs_ioapic_data {

5
arch/x86/pci/acpi.c
View File

@ -250,10 +250,5 @@ int __init pci_acpi_init(void)
acpi_pci_irq_enable(dev);
}
#ifdef CONFIG_X86_IO_APIC
if (acpi_ioapic)
print_IO_APIC();
#endif
return 0;
}

1
include/asm-x86/hw_irq.h
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@ -64,7 +64,6 @@ extern unsigned long io_apic_irqs;
extern void init_VISWS_APIC_irqs(void);
extern void setup_IO_APIC(void);
extern void disable_IO_APIC(void);
extern void print_IO_APIC(void);
extern int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn);
extern void setup_ioapic_dest(void);