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https://github.com/torvalds/linux.git
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Merge branch 'topic/mv_xor' into for-linus
This commit is contained in:
Vinod Koul
commit
87fce2f5f4
@ -42,6 +42,7 @@
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#define MV_XOR_V2_DMA_IMSG_THRD_OFF 0x018
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#define MV_XOR_V2_DMA_IMSG_THRD_MASK 0x7FFF
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#define MV_XOR_V2_DMA_IMSG_THRD_SHIFT 0x0
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#define MV_XOR_V2_DMA_IMSG_TIMER_EN BIT(18)
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#define MV_XOR_V2_DMA_DESQ_AWATTR_OFF 0x01C
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/* Same flags as MV_XOR_V2_DMA_DESQ_ARATTR_OFF */
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#define MV_XOR_V2_DMA_DESQ_ALLOC_OFF 0x04C
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@ -55,6 +56,9 @@
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#define MV_XOR_V2_DMA_DESQ_STOP_OFF 0x800
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#define MV_XOR_V2_DMA_DESQ_DEALLOC_OFF 0x804
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#define MV_XOR_V2_DMA_DESQ_ADD_OFF 0x808
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#define MV_XOR_V2_DMA_IMSG_TMOT 0x810
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#define MV_XOR_V2_DMA_IMSG_TIMER_THRD_MASK 0x1FFF
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#define MV_XOR_V2_DMA_IMSG_TIMER_THRD_SHIFT 0
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/* XOR Global registers */
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#define MV_XOR_V2_GLOB_BW_CTRL 0x4
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@ -90,6 +94,13 @@
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*/
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#define MV_XOR_V2_DESC_NUM 1024
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/*
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* Threshold values for descriptors and timeout, determined by
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* experimentation as giving a good level of performance.
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*/
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#define MV_XOR_V2_DONE_IMSG_THRD 0x14
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#define MV_XOR_V2_TIMER_THRD 0xB0
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/**
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* struct mv_xor_v2_descriptor - DMA HW descriptor
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* @desc_id: used by S/W and is not affected by H/W.
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@ -161,6 +172,7 @@ struct mv_xor_v2_device {
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struct mv_xor_v2_sw_desc *sw_desq;
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int desc_size;
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unsigned int npendings;
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unsigned int hw_queue_idx;
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};
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/**
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@ -213,18 +225,6 @@ static void mv_xor_v2_set_data_buffers(struct mv_xor_v2_device *xor_dev,
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}
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}
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/*
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* Return the next available index in the DESQ.
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*/
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static int mv_xor_v2_get_desq_write_ptr(struct mv_xor_v2_device *xor_dev)
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{
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/* read the index for the next available descriptor in the DESQ */
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u32 reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_ALLOC_OFF);
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return ((reg >> MV_XOR_V2_DMA_DESQ_ALLOC_WRPTR_SHIFT)
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& MV_XOR_V2_DMA_DESQ_ALLOC_WRPTR_MASK);
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}
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/*
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* notify the engine of new descriptors, and update the available index.
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*/
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@ -261,16 +261,23 @@ static int mv_xor_v2_set_desc_size(struct mv_xor_v2_device *xor_dev)
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* Set the IMSG threshold
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*/
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static inline
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void mv_xor_v2_set_imsg_thrd(struct mv_xor_v2_device *xor_dev, int thrd_val)
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void mv_xor_v2_enable_imsg_thrd(struct mv_xor_v2_device *xor_dev)
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{
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u32 reg;
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/* Configure threshold of number of descriptors, and enable timer */
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reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_THRD_OFF);
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reg &= (~MV_XOR_V2_DMA_IMSG_THRD_MASK << MV_XOR_V2_DMA_IMSG_THRD_SHIFT);
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reg |= (thrd_val << MV_XOR_V2_DMA_IMSG_THRD_SHIFT);
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reg |= (MV_XOR_V2_DONE_IMSG_THRD << MV_XOR_V2_DMA_IMSG_THRD_SHIFT);
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reg |= MV_XOR_V2_DMA_IMSG_TIMER_EN;
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writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_THRD_OFF);
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/* Configure Timer Threshold */
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reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_TMOT);
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reg &= (~MV_XOR_V2_DMA_IMSG_TIMER_THRD_MASK <<
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MV_XOR_V2_DMA_IMSG_TIMER_THRD_SHIFT);
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reg |= (MV_XOR_V2_TIMER_THRD << MV_XOR_V2_DMA_IMSG_TIMER_THRD_SHIFT);
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writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_TMOT);
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}
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static irqreturn_t mv_xor_v2_interrupt_handler(int irq, void *data)
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@ -288,12 +295,6 @@ static irqreturn_t mv_xor_v2_interrupt_handler(int irq, void *data)
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if (!ndescs)
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return IRQ_NONE;
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/*
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* Update IMSG threshold, to disable new IMSG interrupts until
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* end of the tasklet
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*/
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mv_xor_v2_set_imsg_thrd(xor_dev, MV_XOR_V2_DESC_NUM);
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/* schedule a tasklet to handle descriptors callbacks */
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tasklet_schedule(&xor_dev->irq_tasklet);
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@ -306,7 +307,6 @@ static irqreturn_t mv_xor_v2_interrupt_handler(int irq, void *data)
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static dma_cookie_t
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mv_xor_v2_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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int desq_ptr;
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void *dest_hw_desc;
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dma_cookie_t cookie;
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struct mv_xor_v2_sw_desc *sw_desc =
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@ -322,15 +322,15 @@ mv_xor_v2_tx_submit(struct dma_async_tx_descriptor *tx)
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spin_lock_bh(&xor_dev->lock);
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cookie = dma_cookie_assign(tx);
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/* get the next available slot in the DESQ */
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desq_ptr = mv_xor_v2_get_desq_write_ptr(xor_dev);
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/* copy the HW descriptor from the SW descriptor to the DESQ */
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dest_hw_desc = xor_dev->hw_desq_virt + desq_ptr;
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dest_hw_desc = xor_dev->hw_desq_virt + xor_dev->hw_queue_idx;
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memcpy(dest_hw_desc, &sw_desc->hw_desc, xor_dev->desc_size);
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xor_dev->npendings++;
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xor_dev->hw_queue_idx++;
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if (xor_dev->hw_queue_idx >= MV_XOR_V2_DESC_NUM)
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xor_dev->hw_queue_idx = 0;
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spin_unlock_bh(&xor_dev->lock);
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@ -344,6 +344,7 @@ static struct mv_xor_v2_sw_desc *
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mv_xor_v2_prep_sw_desc(struct mv_xor_v2_device *xor_dev)
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{
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struct mv_xor_v2_sw_desc *sw_desc;
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bool found = false;
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/* Lock the channel */
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spin_lock_bh(&xor_dev->lock);
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@ -355,19 +356,23 @@ mv_xor_v2_prep_sw_desc(struct mv_xor_v2_device *xor_dev)
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return NULL;
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}
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/* get a free SW descriptor from the SW DESQ */
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sw_desc = list_first_entry(&xor_dev->free_sw_desc,
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struct mv_xor_v2_sw_desc, free_list);
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list_for_each_entry(sw_desc, &xor_dev->free_sw_desc, free_list) {
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if (async_tx_test_ack(&sw_desc->async_tx)) {
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found = true;
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break;
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}
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}
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if (!found) {
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spin_unlock_bh(&xor_dev->lock);
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return NULL;
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}
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list_del(&sw_desc->free_list);
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/* Release the channel */
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spin_unlock_bh(&xor_dev->lock);
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/* set the async tx descriptor */
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dma_async_tx_descriptor_init(&sw_desc->async_tx, &xor_dev->dmachan);
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sw_desc->async_tx.tx_submit = mv_xor_v2_tx_submit;
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async_tx_ack(&sw_desc->async_tx);
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return sw_desc;
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}
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@ -389,6 +394,8 @@ mv_xor_v2_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest,
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__func__, len, &src, &dest, flags);
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sw_desc = mv_xor_v2_prep_sw_desc(xor_dev);
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if (!sw_desc)
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return NULL;
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sw_desc->async_tx.flags = flags;
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@ -443,6 +450,8 @@ mv_xor_v2_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
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__func__, src_cnt, len, &dest, flags);
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sw_desc = mv_xor_v2_prep_sw_desc(xor_dev);
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if (!sw_desc)
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return NULL;
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sw_desc->async_tx.flags = flags;
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@ -491,6 +500,8 @@ mv_xor_v2_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
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container_of(chan, struct mv_xor_v2_device, dmachan);
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sw_desc = mv_xor_v2_prep_sw_desc(xor_dev);
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if (!sw_desc)
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return NULL;
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/* set the HW descriptor */
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hw_descriptor = &sw_desc->hw_desc;
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@ -524,9 +535,6 @@ static void mv_xor_v2_issue_pending(struct dma_chan *chan)
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mv_xor_v2_add_desc_to_desq(xor_dev, xor_dev->npendings);
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xor_dev->npendings = 0;
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/* Activate the channel */
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writel(0, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_STOP_OFF);
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spin_unlock_bh(&xor_dev->lock);
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}
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@ -554,7 +562,6 @@ static void mv_xor_v2_tasklet(unsigned long data)
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{
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struct mv_xor_v2_device *xor_dev = (struct mv_xor_v2_device *) data;
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int pending_ptr, num_of_pending, i;
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struct mv_xor_v2_descriptor *next_pending_hw_desc = NULL;
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struct mv_xor_v2_sw_desc *next_pending_sw_desc = NULL;
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dev_dbg(xor_dev->dmadev.dev, "%s %d\n", __func__, __LINE__);
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@ -562,17 +569,10 @@ static void mv_xor_v2_tasklet(unsigned long data)
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/* get the pending descriptors parameters */
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num_of_pending = mv_xor_v2_get_pending_params(xor_dev, &pending_ptr);
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/* next HW descriptor */
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next_pending_hw_desc = xor_dev->hw_desq_virt + pending_ptr;
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/* loop over free descriptors */
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for (i = 0; i < num_of_pending; i++) {
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if (pending_ptr > MV_XOR_V2_DESC_NUM)
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pending_ptr = 0;
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if (next_pending_sw_desc != NULL)
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next_pending_hw_desc++;
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struct mv_xor_v2_descriptor *next_pending_hw_desc =
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xor_dev->hw_desq_virt + pending_ptr;
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/* get the SW descriptor related to the HW descriptor */
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next_pending_sw_desc =
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@ -608,15 +608,14 @@ static void mv_xor_v2_tasklet(unsigned long data)
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/* increment the next descriptor */
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pending_ptr++;
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if (pending_ptr >= MV_XOR_V2_DESC_NUM)
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pending_ptr = 0;
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}
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if (num_of_pending != 0) {
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/* free the descriptores */
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mv_xor_v2_free_desc_from_desq(xor_dev, num_of_pending);
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}
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/* Update IMSG threshold, to enable new IMSG interrupts */
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mv_xor_v2_set_imsg_thrd(xor_dev, 0);
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}
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/*
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@ -648,9 +647,6 @@ static int mv_xor_v2_descq_init(struct mv_xor_v2_device *xor_dev)
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writel((xor_dev->hw_desq & 0xFFFF00000000) >> 32,
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xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_BAHR_OFF);
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/* enable the DMA engine */
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writel(0, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_STOP_OFF);
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/*
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* This is a temporary solution, until we activate the
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* SMMU. Set the attributes for reading & writing data buffers
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@ -694,6 +690,30 @@ static int mv_xor_v2_descq_init(struct mv_xor_v2_device *xor_dev)
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reg |= MV_XOR_V2_GLOB_PAUSE_AXI_TIME_DIS_VAL;
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writel(reg, xor_dev->glob_base + MV_XOR_V2_GLOB_PAUSE);
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/* enable the DMA engine */
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writel(0, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_STOP_OFF);
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return 0;
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}
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static int mv_xor_v2_suspend(struct platform_device *dev, pm_message_t state)
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{
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struct mv_xor_v2_device *xor_dev = platform_get_drvdata(dev);
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/* Set this bit to disable to stop the XOR unit. */
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writel(0x1, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_STOP_OFF);
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return 0;
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}
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static int mv_xor_v2_resume(struct platform_device *dev)
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{
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struct mv_xor_v2_device *xor_dev = platform_get_drvdata(dev);
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mv_xor_v2_set_desc_size(xor_dev);
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mv_xor_v2_enable_imsg_thrd(xor_dev);
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mv_xor_v2_descq_init(xor_dev);
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return 0;
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}
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@ -725,6 +745,10 @@ static int mv_xor_v2_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, xor_dev);
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ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
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if (ret)
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return ret;
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xor_dev->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(xor_dev->clk) && PTR_ERR(xor_dev->clk) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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@ -785,8 +809,15 @@ static int mv_xor_v2_probe(struct platform_device *pdev)
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/* add all SW descriptors to the free list */
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for (i = 0; i < MV_XOR_V2_DESC_NUM; i++) {
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xor_dev->sw_desq[i].idx = i;
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list_add(&xor_dev->sw_desq[i].free_list,
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struct mv_xor_v2_sw_desc *sw_desc =
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xor_dev->sw_desq + i;
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sw_desc->idx = i;
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dma_async_tx_descriptor_init(&sw_desc->async_tx,
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&xor_dev->dmachan);
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sw_desc->async_tx.tx_submit = mv_xor_v2_tx_submit;
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async_tx_ack(&sw_desc->async_tx);
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list_add(&sw_desc->free_list,
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&xor_dev->free_sw_desc);
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}
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@ -816,6 +847,8 @@ static int mv_xor_v2_probe(struct platform_device *pdev)
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list_add_tail(&xor_dev->dmachan.device_node,
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&dma_dev->channels);
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mv_xor_v2_enable_imsg_thrd(xor_dev);
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mv_xor_v2_descq_init(xor_dev);
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ret = dma_async_device_register(dma_dev);
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@ -865,6 +898,8 @@ MODULE_DEVICE_TABLE(of, mv_xor_v2_dt_ids);
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static struct platform_driver mv_xor_v2_driver = {
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.probe = mv_xor_v2_probe,
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.suspend = mv_xor_v2_suspend,
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.resume = mv_xor_v2_resume,
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.remove = mv_xor_v2_remove,
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.driver = {
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.name = "mv_xor_v2",
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