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ARM: Optimize multi-CPU tlb flushing a little more
The compiler does not conditionalize the assembly instructions for
the tlb operations, which leads to sub-optimal code being generated
when building a kernel for multiple CPUs.
We can tweak things fairly simply as the code fragment below shows:
17f8: e3120001 tst r2, #1 ; 0x1
...
1800: 0a000000 beq 1808 <handle_pte_fault+0x194>
1804: ee061f10 mcr 15, 0, r1, cr6, cr0, {0}
1808: e3120004 tst r2, #4 ; 0x4
180c: 0a000000 beq 1814 <handle_pte_fault+0x1a0>
1810: ee081f36 mcr 15, 0, r1, cr8, cr6, {1}
becomes:
17f0: e3120001 tst r2, #1 ; 0x1
17f4: 1e063f10 mcrne 15, 0, r3, cr6, cr0, {0}
17f8: e3120004 tst r2, #4 ; 0x4
17fc: 1e083f36 mcrne 15, 0, r3, cr8, cr6, {1}
Overall, for Realview with V6 and V7 CPUs configured:
text data bss dec hex filename
4153998 207340 5371036 9732374 948116 ../build/realview/vmlinux.before
4153366 207332 5371036 9731734 947e96 ../build/realview/vmlinux.after
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
d9277d51a8
commit
87067a935a
@ -318,6 +318,21 @@ extern struct cpu_tlb_fns cpu_tlb;
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#define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
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#define __tlb_op(f, insnarg, arg) \
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do { \
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if (always_tlb_flags & (f)) \
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asm("mcr " insnarg \
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: : "r" (arg) : "cc"); \
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else if (possible_tlb_flags & (f)) \
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asm("tst %1, %2\n\t" \
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"mcrne " insnarg \
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: : "r" (arg), "r" (__tlb_flag), "Ir" (f) \
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: "cc"); \
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} while (0)
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#define tlb_op(f, regs, arg) __tlb_op(f, "p15, 0, %0, " regs, arg)
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#define tlb_l2_op(f, regs, arg) __tlb_op(f, "p15, 1, %0, " regs, arg)
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static inline void local_flush_tlb_all(void)
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{
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const int zero = 0;
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@ -326,16 +341,11 @@ static inline void local_flush_tlb_all(void)
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if (tlb_flag(TLB_WB))
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dsb();
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if (tlb_flag(TLB_V3_FULL))
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asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL))
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asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL))
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asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
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asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V7_UIS_FULL))
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asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
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tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);
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tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero);
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tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero);
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tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero);
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tlb_op(TLB_V7_UIS_FULL, "c8, c3, 0", zero);
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if (tlb_flag(TLB_BARRIER)) {
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dsb();
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@ -352,29 +362,23 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
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if (tlb_flag(TLB_WB))
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dsb();
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if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
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if (tlb_flag(TLB_V3_FULL))
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asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V4_U_FULL))
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asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V4_D_FULL))
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asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V4_I_FULL))
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asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
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if (possible_tlb_flags & (TLB_V3_FULL|TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) {
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if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
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tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);
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tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);
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tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);
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tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
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}
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put_cpu();
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}
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put_cpu();
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if (tlb_flag(TLB_V6_U_ASID))
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asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc");
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if (tlb_flag(TLB_V6_D_ASID))
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asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
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if (tlb_flag(TLB_V6_I_ASID))
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asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
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if (tlb_flag(TLB_V7_UIS_ASID))
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tlb_op(TLB_V6_U_ASID, "c8, c7, 2", asid);
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tlb_op(TLB_V6_D_ASID, "c8, c6, 2", asid);
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tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid);
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#ifdef CONFIG_ARM_ERRATA_720789
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asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
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tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", zero);
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#else
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asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc");
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tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", asid);
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#endif
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if (tlb_flag(TLB_BARRIER))
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@ -392,30 +396,23 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
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if (tlb_flag(TLB_WB))
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dsb();
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if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
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if (tlb_flag(TLB_V3_PAGE))
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asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_V4_U_PAGE))
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asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_V4_D_PAGE))
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asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_V4_I_PAGE))
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asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
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if (possible_tlb_flags & (TLB_V3_PAGE|TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) &&
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cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
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tlb_op(TLB_V3_PAGE, "c6, c0, 0", uaddr);
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tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr);
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tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr);
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tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr);
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if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
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asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
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}
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if (tlb_flag(TLB_V6_U_PAGE))
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asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_V6_D_PAGE))
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asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_V6_I_PAGE))
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asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_V7_UIS_PAGE))
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tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", uaddr);
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tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", uaddr);
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tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr);
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#ifdef CONFIG_ARM_ERRATA_720789
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asm("mcr p15, 0, %0, c8, c3, 3" : : "r" (uaddr & PAGE_MASK) : "cc");
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tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 3", uaddr & PAGE_MASK);
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#else
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asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc");
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tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", uaddr);
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#endif
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if (tlb_flag(TLB_BARRIER))
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@ -432,25 +429,17 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
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if (tlb_flag(TLB_WB))
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dsb();
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if (tlb_flag(TLB_V3_PAGE))
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asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_V4_U_PAGE))
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asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_V4_D_PAGE))
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asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_V4_I_PAGE))
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asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
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tlb_op(TLB_V3_PAGE, "c6, c0, 0", kaddr);
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tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr);
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tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr);
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tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr);
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if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
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asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V6_U_PAGE))
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asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_V6_D_PAGE))
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asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_V6_I_PAGE))
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asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_V7_UIS_PAGE))
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asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc");
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tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", kaddr);
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tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", kaddr);
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tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr);
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tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", kaddr);
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if (tlb_flag(TLB_BARRIER)) {
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dsb();
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@ -475,13 +464,8 @@ static inline void flush_pmd_entry(void *pmd)
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{
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const unsigned int __tlb_flag = __cpu_tlb_flags;
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if (tlb_flag(TLB_DCLEAN))
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asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
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: : "r" (pmd) : "cc");
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if (tlb_flag(TLB_L2CLEAN_FR))
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asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd"
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: : "r" (pmd) : "cc");
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tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd);
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tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd);
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if (tlb_flag(TLB_WB))
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dsb();
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@ -491,15 +475,11 @@ static inline void clean_pmd_entry(void *pmd)
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{
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const unsigned int __tlb_flag = __cpu_tlb_flags;
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if (tlb_flag(TLB_DCLEAN))
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asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
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: : "r" (pmd) : "cc");
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if (tlb_flag(TLB_L2CLEAN_FR))
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asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd"
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: : "r" (pmd) : "cc");
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tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd);
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tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd);
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}
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#undef tlb_op
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#undef tlb_flag
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#undef always_tlb_flags
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#undef possible_tlb_flags
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