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UniPhier ARM SoC DT updates for v4.20
- Add more clocks to NAND controller nodes - Add SPI controller nodes - Add SD controller nodes - Add USB 3.0 and its PHY nodes - Add PHY nodes for USB 2.0 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJbtWLqAAoJED2LAQed4NsGES8P/2+T5horfJ9vZ8BQzv1Y4peV PZrIXNJGJtjtCZbYy2mMlwNqGHpsMSE6udGBsT/M4lVoUhAfd+H2kAHytoKRh/Jc lA3bvDnIv3iY7l0L0pQxJ2ADlyGH5Jw7XxZdTWDM7OPljfro1do4XovOZzrz8jgb hQvi2WtIkl3pLrhIBEObv0J/h7/bp3ssYTcireUWXgcJK2Mr55aY3BOZ91SojMwI 4T8z7N6/wszvQX1rZdczOD9oblNIr604kmukhd2wWrhEKbrY9psCYeAHQTWvQ0UU GlhhOeojmsbEKjlqVQEA7+3Fccqq13ieaahFYP1SCYi647owNLTvq9zuO4ElQ+bC +eGt+eVmDYIM8giQEC5s4xmNqqXAgTIK0nPv27Hi7VHlrwY0bjbRXTm1fgSiNPyF 3M587LMoOa2iQJbcO7RE7nHgAmiu7jqx+6I8iw+d6AyiHLq2kJNNGz0SE5XeBgsj pVrksz5wlPi+VzmjwtvUy0EUR7sr6mQtmsjt6i+Z3GdK28bRoNqXezShZ1cpjDiD Dsfx5qm4bn92LiE97tUAefa27GejScCA9TelGFwfvuKRKrb5R1mlU4Wp+65I9gce 4cH0csYWKw/BDyQX2i7yQ2nNB9/VcNRp7qtizU8Ib8YxBNXpx7mjLUU1/LB4bo6h YY3e/IJPVR+JQzFZ7Nl3 =9/hA -----END PGP SIGNATURE----- Merge tag 'uniphier-dt-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt UniPhier ARM SoC DT updates for v4.20 - Add more clocks to NAND controller nodes - Add SPI controller nodes - Add SD controller nodes - Add USB 3.0 and its PHY nodes - Add PHY nodes for USB 2.0 * tag 'uniphier-dt-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: arm64: dts: uniphier: Add USB2 PHY nodes arm64: dts: uniphier: Add USB3 controller nodes ARM: dts: uniphier: Add USB2 PHY nodes ARM: dts: uniphier: Add USB3 controller nodes arm64: dts: uniphier: add SD controller nodes ARM: dts: uniphier: add SD/eMMC controller nodes arm64: dts: uniphier: add SPI node for LD20, LD11 and PXs3 ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCs ARM: dts: uniphier: add SPI pin-mux node arm64: uniphier: dts: add more clocks to Denali NAND controller node ARM: uniphier: dts: add more clocks to Denali NAND controller node Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
86dc4eaf12
@ -63,6 +63,10 @@
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status = "okay";
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};
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&sd {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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@ -63,6 +63,17 @@
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cache-level = <2>;
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||||
};
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spi: spi@54006000 {
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compatible = "socionext,uniphier-scssi";
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status = "disabled";
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reg = <0x54006000 0x100>;
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interrupts = <0 39 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi0>;
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clocks = <&peri_clk 11>;
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resets = <&peri_rst 11>;
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};
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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@ -224,6 +235,40 @@
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};
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};
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sd: sdhc@5a400000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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reg = <0x5a400000 0x200>;
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interrupts = <0 76 4>;
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pinctrl-names = "default", "uhs";
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pinctrl-0 = <&pinctrl_sd>;
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pinctrl-1 = <&pinctrl_sd_uhs>;
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clocks = <&mio_clk 0>;
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reset-names = "host", "bridge";
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resets = <&mio_rst 0>, <&mio_rst 3>;
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bus-width = <4>;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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};
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emmc: sdhc@5a500000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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reg = <0x5a500000 0x200>;
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interrupts = <0 78 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_emmc>;
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clocks = <&mio_clk 1>;
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reset-names = "host", "bridge", "hw";
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resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
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bus-width = <8>;
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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non-removable;
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};
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usb0: usb@5a800100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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@ -347,7 +392,8 @@
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interrupts = <0 65 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand2cs>;
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clocks = <&sys_clk 2>;
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clock-names = "nand", "nand_x", "ecc";
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clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
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resets = <&sys_rst 2>;
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};
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};
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@ -65,6 +65,10 @@
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status = "okay";
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};
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&sd {
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status = "okay";
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};
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ð {
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status = "okay";
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phy-handle = <ðphy>;
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@ -76,6 +80,14 @@
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};
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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&nand {
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status = "okay";
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};
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@ -121,11 +121,36 @@
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function = "sd";
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};
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pinctrl_sd_uhs: sd-uhs {
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groups = "sd";
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function = "sd";
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};
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pinctrl_sd1: sd1 {
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groups = "sd1";
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function = "sd1";
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};
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pinctrl_spi0: spi0 {
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groups = "spi0";
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function = "spi0";
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};
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pinctrl_spi1: spi1 {
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groups = "spi1";
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function = "spi1";
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};
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pinctrl_spi2: spi2 {
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groups = "spi2";
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function = "spi2";
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};
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pinctrl_spi3: spi3 {
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groups = "spi3";
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function = "spi3";
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};
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pinctrl_system_bus: system-bus {
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groups = "system_bus", "system_bus_cs1";
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function = "system_bus";
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@ -68,6 +68,10 @@
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status = "okay";
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};
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&sd {
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status = "okay";
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};
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&usb2 {
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status = "okay";
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};
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@ -86,3 +90,11 @@
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reg = <1>;
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};
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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@ -65,6 +65,10 @@
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status = "okay";
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};
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&sd {
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status = "okay";
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};
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&usb2 {
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status = "okay";
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};
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@ -84,6 +88,14 @@
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};
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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&nand {
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status = "okay";
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};
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@ -71,6 +71,10 @@
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status = "okay";
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};
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&emmc {
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status = "okay";
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};
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ð {
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status = "okay";
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phy-handle = <ðphy>;
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@ -81,3 +85,11 @@
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reg = <1>;
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};
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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@ -71,6 +71,17 @@
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cache-level = <2>;
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};
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spi0: spi@54006000 {
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compatible = "socionext,uniphier-scssi";
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status = "disabled";
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reg = <0x54006000 0x100>;
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interrupts = <0 39 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi0>;
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clocks = <&peri_clk 11>;
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resets = <&peri_rst 11>;
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};
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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@ -258,6 +269,54 @@
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};
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};
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sd: sdhc@5a400000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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reg = <0x5a400000 0x200>;
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interrupts = <0 76 4>;
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pinctrl-names = "default", "uhs";
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pinctrl-0 = <&pinctrl_sd>;
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pinctrl-1 = <&pinctrl_sd_uhs>;
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clocks = <&mio_clk 0>;
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reset-names = "host", "bridge";
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resets = <&mio_rst 0>, <&mio_rst 3>;
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bus-width = <4>;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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};
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emmc: sdhc@5a500000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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reg = <0x5a500000 0x200>;
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interrupts = <0 78 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_emmc>;
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clocks = <&mio_clk 1>;
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reset-names = "host", "bridge", "hw";
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resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
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bus-width = <8>;
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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non-removable;
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};
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sd1: sdhc@5a600000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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reg = <0x5a600000 0x200>;
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interrupts = <0 85 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sd1>;
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clocks = <&mio_clk 2>;
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reset-names = "host", "bridge";
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resets = <&mio_rst 2>, <&mio_rst 5>;
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bus-width = <4>;
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cap-sd-highspeed;
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};
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usb2: usb@5a800100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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@ -269,6 +328,8 @@
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<&mio_clk 12>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
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<&mio_rst 12>;
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phy-names = "usb";
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phys = <&usb_phy0>;
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has-transaction-translator;
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};
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@ -283,6 +344,8 @@
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<&mio_clk 13>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
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<&mio_rst 13>;
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phy-names = "usb";
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phys = <&usb_phy1>;
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has-transaction-translator;
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};
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@ -294,6 +357,34 @@
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pinctrl: pinctrl {
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compatible = "socionext,uniphier-pro4-pinctrl";
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};
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usb-phy {
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compatible = "socionext,uniphier-pro4-usb2-phy";
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#address-cells = <1>;
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#size-cells = <0>;
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usb_phy0: phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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};
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usb_phy1: phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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};
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usb_phy2: phy@2 {
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reg = <2>;
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#phy-cells = <0>;
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vbus-supply = <&usb0_vbus>;
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};
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usb_phy3: phy@3 {
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reg = <3>;
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#phy-cells = <0>;
|
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vbus-supply = <&usb1_vbus>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc-glue@5f900000 {
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@ -386,6 +477,101 @@
|
||||
};
|
||||
};
|
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usb0: usb@65a00000 {
|
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compatible = "socionext,uniphier-dwc3", "snps,dwc3";
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status = "disabled";
|
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reg = <0x65a00000 0xcd00>;
|
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interrupt-names = "host", "peripheral";
|
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interrupts = <0 134 4>, <0 135 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>;
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clock-names = "ref", "bus_early", "suspend";
|
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clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
|
||||
resets = <&usb0_rst 4>;
|
||||
phys = <&usb_phy2>, <&usb0_ssphy>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65b00000 {
|
||||
compatible = "socionext,uniphier-pro4-dwc3-glue",
|
||||
"simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65b00000 0x100>;
|
||||
|
||||
usb0_vbus: regulator@0 {
|
||||
compatible = "socionext,uniphier-pro4-usb3-regulator";
|
||||
reg = <0 0x10>;
|
||||
clock-names = "gio", "link";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 14>;
|
||||
reset-names = "gio", "link";
|
||||
resets = <&sys_rst 12>, <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb0_ssphy: ss-phy@10 {
|
||||
compatible = "socionext,uniphier-pro4-usb3-ssphy";
|
||||
reg = <0x10 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "gio", "link";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 14>;
|
||||
reset-names = "gio", "link";
|
||||
resets = <&sys_rst 12>, <&sys_rst 14>;
|
||||
vbus-supply = <&usb0_vbus>;
|
||||
};
|
||||
|
||||
usb0_rst: reset@40 {
|
||||
compatible = "socionext,uniphier-pro4-usb3-reset";
|
||||
reg = <0x40 0x4>;
|
||||
#reset-cells = <1>;
|
||||
clock-names = "gio", "link";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 14>;
|
||||
reset-names = "gio", "link";
|
||||
resets = <&sys_rst 12>, <&sys_rst 14>;
|
||||
};
|
||||
};
|
||||
|
||||
usb1: usb@65c00000 {
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65c00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 137 4>, <0 138 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
|
||||
resets = <&usb1_rst 4>;
|
||||
phys = <&usb_phy3>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65d00000 {
|
||||
compatible = "socionext,uniphier-pro4-dwc3-glue",
|
||||
"simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65d00000 0x100>;
|
||||
|
||||
usb1_vbus: regulator@0 {
|
||||
compatible = "socionext,uniphier-pro4-usb3-regulator";
|
||||
reg = <0 0x10>;
|
||||
clock-names = "gio", "link";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 15>;
|
||||
reset-names = "gio", "link";
|
||||
resets = <&sys_rst 12>, <&sys_rst 15>;
|
||||
};
|
||||
|
||||
usb1_rst: reset@40 {
|
||||
compatible = "socionext,uniphier-pro4-usb3-reset";
|
||||
reg = <0x40 0x4>;
|
||||
#reset-cells = <1>;
|
||||
clock-names = "gio", "link";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 15>;
|
||||
reset-names = "gio", "link";
|
||||
resets = <&sys_rst 12>, <&sys_rst 15>;
|
||||
};
|
||||
};
|
||||
|
||||
nand: nand@68000000 {
|
||||
compatible = "socionext,uniphier-denali-nand-v5a";
|
||||
status = "disabled";
|
||||
@ -394,7 +580,8 @@
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
clocks = <&sys_clk 2>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -156,6 +156,28 @@
|
||||
cache-level = <3>;
|
||||
};
|
||||
|
||||
spi0: spi@54006000 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006000 0x100>;
|
||||
interrupts = <0 39 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
spi1: spi@54006100 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006100 0x100>;
|
||||
interrupts = <0 216 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
@ -439,9 +461,44 @@
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand2cs>;
|
||||
clocks = <&sys_clk 2>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
};
|
||||
|
||||
emmc: sdhc@68400000 {
|
||||
compatible = "socionext,uniphier-sd-v3.1";
|
||||
status = "disabled";
|
||||
reg = <0x68400000 0x800>;
|
||||
interrupts = <0 78 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_emmc>;
|
||||
clocks = <&sd_clk 1>;
|
||||
reset-names = "host", "hw";
|
||||
resets = <&sd_rst 1>, <&sd_rst 6>;
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
cap-mmc-hw-reset;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
sd: sdhc@68800000 {
|
||||
compatible = "socionext,uniphier-sd-v3.1";
|
||||
status = "disabled";
|
||||
reg = <0x68800000 0x800>;
|
||||
interrupts = <0 76 4>;
|
||||
pinctrl-names = "default", "uhs";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
pinctrl-1 = <&pinctrl_sd_uhs>;
|
||||
clocks = <&sd_clk 0>;
|
||||
reset-names = "host";
|
||||
resets = <&sd_rst 0>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -76,6 +76,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
&emmc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð {
|
||||
status = "okay";
|
||||
phy-handle = <ðphy>;
|
||||
@ -86,3 +90,11 @@
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -77,6 +77,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&emmc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð {
|
||||
status = "okay";
|
||||
phy-handle = <ðphy>;
|
||||
@ -87,3 +91,7 @@
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -167,6 +167,28 @@
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
spi0: spi@54006000 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006000 0x100>;
|
||||
interrupts = <0 39 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
spi1: spi@54006100 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006100 0x100>;
|
||||
interrupts = <0 216 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
@ -422,6 +444,40 @@
|
||||
};
|
||||
};
|
||||
|
||||
emmc: sdhc@5a000000 {
|
||||
compatible = "socionext,uniphier-sd-v3.1.1";
|
||||
status = "disabled";
|
||||
reg = <0x5a000000 0x800>;
|
||||
interrupts = <0 78 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_emmc>;
|
||||
clocks = <&sd_clk 1>;
|
||||
reset-names = "host", "hw";
|
||||
resets = <&sd_rst 1>, <&sd_rst 6>;
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
cap-mmc-hw-reset;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
sd: sdhc@5a400000 {
|
||||
compatible = "socionext,uniphier-sd-v3.1.1";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x800>;
|
||||
interrupts = <0 76 4>;
|
||||
pinctrl-names = "default", "uhs";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
pinctrl-1 = <&pinctrl_sd_uhs>;
|
||||
clocks = <&sd_clk 0>;
|
||||
reset-names = "host";
|
||||
resets = <&sd_rst 0>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
};
|
||||
|
||||
soc_glue: soc-glue@5f800000 {
|
||||
compatible = "socionext,uniphier-pxs2-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
@ -523,6 +579,186 @@
|
||||
};
|
||||
};
|
||||
|
||||
usb0: usb@65a00000 {
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65a00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 134 4>, <0 135 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
|
||||
resets = <&usb0_rst 15>;
|
||||
phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
|
||||
<&usb0_ssphy0>, <&usb0_ssphy1>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65b00000 {
|
||||
compatible = "socionext,uniphier-pxs2-dwc3-glue",
|
||||
"simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65b00000 0x400>;
|
||||
|
||||
usb0_rst: reset@0 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 14>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb0_vbus0: regulator@100 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-regulator";
|
||||
reg = <0x100 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 14>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb0_vbus1: regulator@110 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-regulator";
|
||||
reg = <0x110 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 14>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb0_hsphy0: hs-phy@200 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
|
||||
reg = <0x200 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 16>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 16>;
|
||||
vbus-supply = <&usb0_vbus0>;
|
||||
};
|
||||
|
||||
usb0_hsphy1: hs-phy@210 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
|
||||
reg = <0x210 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 16>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 16>;
|
||||
vbus-supply = <&usb0_vbus1>;
|
||||
};
|
||||
|
||||
usb0_ssphy0: ss-phy@300 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
|
||||
reg = <0x300 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 17>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 17>;
|
||||
vbus-supply = <&usb0_vbus0>;
|
||||
};
|
||||
|
||||
usb0_ssphy1: ss-phy@310 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
|
||||
reg = <0x310 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 18>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 18>;
|
||||
vbus-supply = <&usb0_vbus1>;
|
||||
};
|
||||
};
|
||||
|
||||
usb1: usb@65c00000 {
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65c00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 137 4>, <0 138 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>;
|
||||
resets = <&usb1_rst 15>;
|
||||
phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65d00000 {
|
||||
compatible = "socionext,uniphier-pxs2-dwc3-glue",
|
||||
"simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65d00000 0x400>;
|
||||
|
||||
usb1_rst: reset@0 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 15>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 15>;
|
||||
};
|
||||
|
||||
usb1_vbus0: regulator@100 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-regulator";
|
||||
reg = <0x100 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 15>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 15>;
|
||||
};
|
||||
|
||||
usb1_vbus1: regulator@110 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-regulator";
|
||||
reg = <0x110 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 15>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 15>;
|
||||
};
|
||||
|
||||
usb1_hsphy0: hs-phy@200 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
|
||||
reg = <0x200 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 15>, <&sys_clk 20>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 15>, <&sys_rst 20>;
|
||||
vbus-supply = <&usb1_vbus0>;
|
||||
};
|
||||
|
||||
usb1_hsphy1: hs-phy@210 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
|
||||
reg = <0x210 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 15>, <&sys_clk 20>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 15>, <&sys_rst 20>;
|
||||
vbus-supply = <&usb1_vbus1>;
|
||||
};
|
||||
|
||||
usb1_ssphy0: ss-phy@300 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
|
||||
reg = <0x300 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 15>, <&sys_clk 21>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 15>, <&sys_rst 21>;
|
||||
vbus-supply = <&usb1_vbus0>;
|
||||
};
|
||||
};
|
||||
|
||||
nand: nand@68000000 {
|
||||
compatible = "socionext,uniphier-denali-nand-v5b";
|
||||
status = "disabled";
|
||||
@ -531,7 +767,8 @@
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand2cs>;
|
||||
clocks = <&sys_clk 2>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -63,6 +63,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sd {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -63,6 +63,17 @@
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
spi: spi@54006000 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006000 0x100>;
|
||||
interrupts = <0 39 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
@ -228,6 +239,40 @@
|
||||
};
|
||||
};
|
||||
|
||||
sd: sdhc@5a400000 {
|
||||
compatible = "socionext,uniphier-sd-v2.91";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x200>;
|
||||
interrupts = <0 76 4>;
|
||||
pinctrl-names = "default", "uhs";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
pinctrl-1 = <&pinctrl_sd_uhs>;
|
||||
clocks = <&mio_clk 0>;
|
||||
reset-names = "host", "bridge";
|
||||
resets = <&mio_rst 0>, <&mio_rst 3>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
};
|
||||
|
||||
emmc: sdhc@5a500000 {
|
||||
compatible = "socionext,uniphier-sd-v2.91";
|
||||
status = "disabled";
|
||||
reg = <0x5a500000 0x200>;
|
||||
interrupts = <0 78 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_emmc>;
|
||||
clocks = <&mio_clk 1>;
|
||||
reset-names = "host", "bridge", "hw";
|
||||
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
cap-mmc-hw-reset;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
usb0: usb@5a800100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
@ -351,7 +396,8 @@
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand2cs>;
|
||||
clocks = <&sys_clk 2>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -116,6 +116,28 @@
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
|
||||
spi0: spi@54006000 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006000 0x100>;
|
||||
interrupts = <0 39 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
spi1: spi@54006100 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006100 0x100>;
|
||||
interrupts = <0 216 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
@ -432,6 +454,8 @@
|
||||
<&mio_clk 12>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
|
||||
<&mio_rst 12>;
|
||||
phy-names = "usb";
|
||||
phys = <&usb_phy0>;
|
||||
has-transaction-translator;
|
||||
};
|
||||
|
||||
@ -446,6 +470,8 @@
|
||||
<&mio_clk 13>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
|
||||
<&mio_rst 13>;
|
||||
phy-names = "usb";
|
||||
phys = <&usb_phy1>;
|
||||
has-transaction-translator;
|
||||
};
|
||||
|
||||
@ -460,6 +486,8 @@
|
||||
<&mio_clk 14>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
|
||||
<&mio_rst 14>;
|
||||
phy-names = "usb";
|
||||
phys = <&usb_phy2>;
|
||||
has-transaction-translator;
|
||||
};
|
||||
|
||||
@ -488,6 +516,27 @@
|
||||
pinctrl: pinctrl {
|
||||
compatible = "socionext,uniphier-ld11-pinctrl";
|
||||
};
|
||||
|
||||
usb-phy {
|
||||
compatible = "socionext,uniphier-ld11-usb2-phy";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb_phy0: phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
usb_phy1: phy@1 {
|
||||
reg = <1>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
usb_phy2: phy@2 {
|
||||
reg = <2>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc-glue@5f900000 {
|
||||
@ -571,7 +620,8 @@
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
clocks = <&sys_clk 2>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -148,3 +148,7 @@
|
||||
&nand {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -75,3 +75,7 @@
|
||||
drive-strength = <9>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -224,6 +224,50 @@
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
|
||||
spi0: spi@54006000 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006000 0x100>;
|
||||
interrupts = <0 39 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
spi1: spi@54006100 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006100 0x100>;
|
||||
interrupts = <0 216 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
spi2: spi@54006200 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006200 0x100>;
|
||||
interrupts = <0 229 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi2>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
spi3: spi@54006300 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006300 0x100>;
|
||||
interrupts = <0 230 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi3>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
@ -528,6 +572,20 @@
|
||||
cdns,phy-dll-delay-sdclk-hsmmc = <21>;
|
||||
};
|
||||
|
||||
sd: sdhc@5a400000 {
|
||||
compatible = "socionext,uniphier-sd-v3.1.1";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x800>;
|
||||
interrupts = <0 76 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
clocks = <&sd_clk 0>;
|
||||
reset-names = "host";
|
||||
resets = <&sd_rst 0>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
};
|
||||
|
||||
soc_glue: soc-glue@5f800000 {
|
||||
compatible = "socionext,uniphier-ld20-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
@ -553,6 +611,50 @@
|
||||
efuse@200 {
|
||||
compatible = "socionext,uniphier-efuse";
|
||||
reg = <0x200 0x68>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* USB cells */
|
||||
usb_rterm0: trim@54,4 {
|
||||
reg = <0x54 1>;
|
||||
bits = <4 2>;
|
||||
};
|
||||
usb_rterm1: trim@55,4 {
|
||||
reg = <0x55 1>;
|
||||
bits = <4 2>;
|
||||
};
|
||||
usb_rterm2: trim@58,4 {
|
||||
reg = <0x58 1>;
|
||||
bits = <4 2>;
|
||||
};
|
||||
usb_rterm3: trim@59,4 {
|
||||
reg = <0x59 1>;
|
||||
bits = <4 2>;
|
||||
};
|
||||
usb_sel_t0: trim@54,0 {
|
||||
reg = <0x54 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_sel_t1: trim@55,0 {
|
||||
reg = <0x55 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_sel_t2: trim@58,0 {
|
||||
reg = <0x58 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_sel_t3: trim@59,0 {
|
||||
reg = <0x59 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_hs_i0: trim@56,0 {
|
||||
reg = <0x56 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_hs_i2: trim@5a,0 {
|
||||
reg = <0x5a 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -620,6 +722,156 @@
|
||||
};
|
||||
};
|
||||
|
||||
usb: usb@65a00000 {
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65a00000 0xcd00>;
|
||||
interrupt-names = "host";
|
||||
interrupts = <0 134 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
|
||||
<&pinctrl_usb2>, <&pinctrl_usb3>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
|
||||
resets = <&usb_rst 15>;
|
||||
phys = <&usb_hsphy0>, <&usb_hsphy1>,
|
||||
<&usb_hsphy2>, <&usb_hsphy3>,
|
||||
<&usb_ssphy0>, <&usb_ssphy1>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65b00000 {
|
||||
compatible = "socionext,uniphier-ld20-dwc3-glue",
|
||||
"simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65b00000 0x400>;
|
||||
|
||||
usb_rst: reset@0 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 14>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb_vbus0: regulator@100 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-regulator";
|
||||
reg = <0x100 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 14>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb_vbus1: regulator@110 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-regulator";
|
||||
reg = <0x110 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 14>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb_vbus2: regulator@120 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-regulator";
|
||||
reg = <0x120 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 14>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb_vbus3: regulator@130 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-regulator";
|
||||
reg = <0x130 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 14>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb_hsphy0: hs-phy@200 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-hsphy";
|
||||
reg = <0x200 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 16>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 16>;
|
||||
vbus-supply = <&usb_vbus0>;
|
||||
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
||||
nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
|
||||
<&usb_hs_i0>;
|
||||
};
|
||||
|
||||
usb_hsphy1: hs-phy@210 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-hsphy";
|
||||
reg = <0x210 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 16>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 16>;
|
||||
vbus-supply = <&usb_vbus1>;
|
||||
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
||||
nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
|
||||
<&usb_hs_i0>;
|
||||
};
|
||||
|
||||
usb_hsphy2: hs-phy@220 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-hsphy";
|
||||
reg = <0x220 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 17>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 17>;
|
||||
vbus-supply = <&usb_vbus2>;
|
||||
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
||||
nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
|
||||
<&usb_hs_i2>;
|
||||
};
|
||||
|
||||
usb_hsphy3: hs-phy@230 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-hsphy";
|
||||
reg = <0x230 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 17>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 17>;
|
||||
vbus-supply = <&usb_vbus3>;
|
||||
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
||||
nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
|
||||
<&usb_hs_i2>;
|
||||
};
|
||||
|
||||
usb_ssphy0: ss-phy@300 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-ssphy";
|
||||
reg = <0x300 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 18>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 18>;
|
||||
vbus-supply = <&usb_vbus0>;
|
||||
};
|
||||
|
||||
usb_ssphy1: ss-phy@310 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-ssphy";
|
||||
reg = <0x310 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 19>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 19>;
|
||||
vbus-supply = <&usb_vbus1>;
|
||||
};
|
||||
};
|
||||
|
||||
nand: nand@68000000 {
|
||||
compatible = "socionext,uniphier-denali-nand-v5b";
|
||||
status = "disabled";
|
||||
@ -628,7 +880,8 @@
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
clocks = <&sys_clk 2>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -75,6 +75,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sd {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð0 {
|
||||
status = "okay";
|
||||
phy-handle = <ðphy0>;
|
||||
@ -100,3 +104,11 @@
|
||||
&nand {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -144,6 +144,28 @@
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
|
||||
spi0: spi@54006000 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006000 0x100>;
|
||||
interrupts = <0 39 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
spi1: spi@54006100 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006100 0x100>;
|
||||
interrupts = <0 216 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
@ -341,6 +363,24 @@
|
||||
cdns,phy-dll-delay-sdclk-hsmmc = <21>;
|
||||
};
|
||||
|
||||
sd: sdhc@5a400000 {
|
||||
compatible = "socionext,uniphier-sd-v3.1.1";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x800>;
|
||||
interrupts = <0 76 4>;
|
||||
pinctrl-names = "default", "uhs";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
pinctrl-1 = <&pinctrl_sd_uhs>;
|
||||
clocks = <&sd_clk 0>;
|
||||
reset-names = "host";
|
||||
resets = <&sd_rst 0>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
};
|
||||
|
||||
soc_glue: soc-glue@5f800000 {
|
||||
compatible = "socionext,uniphier-pxs3-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
@ -366,6 +406,50 @@
|
||||
efuse@200 {
|
||||
compatible = "socionext,uniphier-efuse";
|
||||
reg = <0x200 0x68>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* USB cells */
|
||||
usb_rterm0: trim@54,4 {
|
||||
reg = <0x54 1>;
|
||||
bits = <4 2>;
|
||||
};
|
||||
usb_rterm1: trim@55,4 {
|
||||
reg = <0x55 1>;
|
||||
bits = <4 2>;
|
||||
};
|
||||
usb_rterm2: trim@58,4 {
|
||||
reg = <0x58 1>;
|
||||
bits = <4 2>;
|
||||
};
|
||||
usb_rterm3: trim@59,4 {
|
||||
reg = <0x59 1>;
|
||||
bits = <4 2>;
|
||||
};
|
||||
usb_sel_t0: trim@54,0 {
|
||||
reg = <0x54 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_sel_t1: trim@55,0 {
|
||||
reg = <0x55 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_sel_t2: trim@58,0 {
|
||||
reg = <0x58 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_sel_t3: trim@59,0 {
|
||||
reg = <0x59 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_hs_i0: trim@56,0 {
|
||||
reg = <0x56 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_hs_i2: trim@5a,0 {
|
||||
reg = <0x5a 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -447,6 +531,202 @@
|
||||
};
|
||||
};
|
||||
|
||||
usb0: usb@65a00000 {
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65a00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 134 4>, <0 135 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
|
||||
resets = <&usb0_rst 15>;
|
||||
phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
|
||||
<&usb0_ssphy0>, <&usb0_ssphy1>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65b00000 {
|
||||
compatible = "socionext,uniphier-pxs3-dwc3-glue",
|
||||
"simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65b00000 0x400>;
|
||||
|
||||
usb0_rst: reset@0 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 12>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 12>;
|
||||
};
|
||||
|
||||
usb0_vbus0: regulator@100 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-regulator";
|
||||
reg = <0x100 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 12>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 12>;
|
||||
};
|
||||
|
||||
usb0_vbus1: regulator@110 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-regulator";
|
||||
reg = <0x110 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 12>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 12>;
|
||||
};
|
||||
|
||||
usb0_hsphy0: hs-phy@200 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
||||
reg = <0x200 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 16>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 12>, <&sys_rst 16>;
|
||||
vbus-supply = <&usb0_vbus0>;
|
||||
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
||||
nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
|
||||
<&usb_hs_i0>;
|
||||
};
|
||||
|
||||
usb0_hsphy1: hs-phy@210 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
||||
reg = <0x210 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 16>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 12>, <&sys_rst 16>;
|
||||
vbus-supply = <&usb0_vbus1>;
|
||||
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
||||
nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
|
||||
<&usb_hs_i0>;
|
||||
};
|
||||
|
||||
usb0_ssphy0: ss-phy@300 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
|
||||
reg = <0x300 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 17>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 12>, <&sys_rst 17>;
|
||||
vbus-supply = <&usb0_vbus0>;
|
||||
};
|
||||
|
||||
usb0_ssphy1: ss-phy@310 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
|
||||
reg = <0x310 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 18>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 12>, <&sys_rst 18>;
|
||||
vbus-supply = <&usb0_vbus1>;
|
||||
};
|
||||
};
|
||||
|
||||
usb1: usb@65c00000 {
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65c00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 137 4>, <0 138 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
|
||||
resets = <&usb1_rst 15>;
|
||||
phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
|
||||
<&usb1_ssphy0>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65d00000 {
|
||||
compatible = "socionext,uniphier-pxs3-dwc3-glue",
|
||||
"simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65d00000 0x400>;
|
||||
|
||||
usb1_rst: reset@0 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 13>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 13>;
|
||||
};
|
||||
|
||||
usb1_vbus0: regulator@100 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-regulator";
|
||||
reg = <0x100 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 13>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 13>;
|
||||
};
|
||||
|
||||
usb1_vbus1: regulator@110 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-regulator";
|
||||
reg = <0x110 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 13>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 13>;
|
||||
};
|
||||
|
||||
usb1_hsphy0: hs-phy@200 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
||||
reg = <0x200 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy", "phy-ext";
|
||||
clocks = <&sys_clk 13>, <&sys_clk 20>,
|
||||
<&sys_clk 14>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 13>, <&sys_rst 20>;
|
||||
vbus-supply = <&usb1_vbus0>;
|
||||
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
||||
nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
|
||||
<&usb_hs_i2>;
|
||||
};
|
||||
|
||||
usb1_hsphy1: hs-phy@210 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
||||
reg = <0x210 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy", "phy-ext";
|
||||
clocks = <&sys_clk 13>, <&sys_clk 20>,
|
||||
<&sys_clk 14>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 13>, <&sys_rst 20>;
|
||||
vbus-supply = <&usb1_vbus1>;
|
||||
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
||||
nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
|
||||
<&usb_hs_i2>;
|
||||
};
|
||||
|
||||
usb1_ssphy0: ss-phy@300 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
|
||||
reg = <0x300 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy", "phy-ext";
|
||||
clocks = <&sys_clk 13>, <&sys_clk 21>,
|
||||
<&sys_clk 14>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 13>, <&sys_rst 21>;
|
||||
vbus-supply = <&usb1_vbus0>;
|
||||
};
|
||||
};
|
||||
|
||||
nand: nand@68000000 {
|
||||
compatible = "socionext,uniphier-denali-nand-v5b";
|
||||
status = "disabled";
|
||||
@ -455,7 +735,8 @@
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
clocks = <&sys_clk 2>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
};
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user