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drm/radeon/kms: fix up DP clock programming on DCE4/5

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In DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
depending on the asic.  The crtc virtual pixel clock is derived from
the DP ref clock.

- DCE4: PPLL or ext clock
- DCE5: DCPLL or ext clock

Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
PPLL/DCPLL programming and only program the DP DTO for the
crtc virtual pixel clock.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher 2011-05-20 04:34:17 -04:00 committed by Dave Airlie
parent 8e8e523d86
commit 86a94defe2
2 changed files with 18 additions and 5 deletions
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12
drivers/gpu/drm/radeon/atombios_crtc.c
View File

@ -1443,11 +1443,19 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
uint32_t pll_in_use = 0; uint32_t pll_in_use = 0;
if (ASIC_IS_DCE4(rdev)) { if (ASIC_IS_DCE4(rdev)) {
/* if crtc is driving DP and we have an ext clock, use that */
list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
if (test_encoder->crtc && (test_encoder->crtc == crtc)) { if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
* depending on the asic:
* DCE4: PPLL or ext clock
* DCE5: DCPLL or ext clock
*
* Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
* PPLL/DCPLL programming and only program the DP DTO for the
* crtc virtual pixel clock.
*/
if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) { if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
if (rdev->clock.dp_extclk) if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
return ATOM_PPLL_INVALID; return ATOM_PPLL_INVALID;
} }
} }

11
drivers/gpu/drm/radeon/radeon_encoders.c
View File

@ -988,11 +988,16 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
} }
if (ASIC_IS_DCE5(rdev)) { if (ASIC_IS_DCE5(rdev)) {
if (is_dp && rdev->clock.dp_extclk) /* On DCE5 DCPLL usually generates the DP ref clock */
args.v4.acConfig.ucRefClkSource = 3; /* external src */ if (is_dp) {
else if (rdev->clock.dp_extclk)
args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
else
args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
} else
args.v4.acConfig.ucRefClkSource = pll_id; args.v4.acConfig.ucRefClkSource = pll_id;
} else { } else {
/* On DCE4, if there is an external clock, it generates the DP ref clock */
if (is_dp && rdev->clock.dp_extclk) if (is_dp && rdev->clock.dp_extclk)
args.v3.acConfig.ucRefClkSource = 2; /* external src */ args.v3.acConfig.ucRefClkSource = 2; /* external src */
else else