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ARM: SoC fixes for v5.7

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This time there is one fix for the error path in the mediatek cmdq driver
 (used by their video driver) and a couple of devicetree fixes, mostly
 for 32-bit ARM, and fairly harmless:
 
 - On OMAP2 there were a few regressions in the ethernet drivers,
   one of them leading to an external abort trap
 
 - One Raspberry Pi version had a misconfigured LED
 
 - Interrupts on Broadcom NSP were slightly misconfigured
 
 - One i.MX6q board had issues with graphics mode setting
 
 - On mmp3 there are some minor fixes that were submitted for
   v5.8 with a cc:stable tag, so I ended up picking them up
   here as well
 
 - The Mediatek Video Codec needs to run at a higher frequency
   than configured originally
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'armsoc-fixes-v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
 "This time there is one fix for the error path in the mediatek cmdq
  driver (used by their video driver) and a couple of devicetree fixes,
  mostly for 32-bit ARM, and fairly harmless:

   - On OMAP2 there were a few regressions in the ethernet drivers, one
     of them leading to an external abort trap

   - One Raspberry Pi version had a misconfigured LED

   - Interrupts on Broadcom NSP were slightly misconfigured

   - One i.MX6q board had issues with graphics mode setting

   - On mmp3 there are some minor fixes that were submitted for v5.8
     with a cc:stable tag, so I ended up picking them up here as well

   - The Mediatek Video Codec needs to run at a higher frequency than
     configured originally"

* tag 'armsoc-fixes-v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  ARM: dts: mmp3: Drop usb-nop-xceiv from HSIC phy
  ARM: dts: mmp3-dell-ariel: Fix the SPI devices
  ARM: dts: mmp3: Use the MMP3 compatible string for /clocks
  ARM: dts: bcm: HR2: Fix PPI interrupt types
  ARM: dts: bcm2835-rpi-zero-w: Fix led polarity
  ARM: dts/imx6q-bx50v3: Set display interface clock parents
  soc: mediatek: cmdq: return send msg error code
  arm64: dts: mt8173: fix vcodec-enc clock
  ARM: dts: Fix wrong mdio clock for dm814x
  ARM: dts: am437x: fix networking on boards with ksz9031 phy
  ARM: dts: am57xx: fix networking on boards with ksz9031 phy
This commit is contained in:
Linus Torvalds 2020-05-29 16:10:07 -07:00
commit 86852175b0
17 changed files with 44 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/am437x-gp-evm.dts
View File

@ -943,7 +943,7 @@
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
};
&elm {

2
arch/arm/boot/dts/am437x-idk-evm.dts
View File

@ -504,7 +504,7 @@
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
};
&rtc {

4
arch/arm/boot/dts/am437x-sk-evm.dts
View File

@ -833,13 +833,13 @@
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy-handle = <&ethphy1>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
dual_emac_res_vlan = <2>;
};

4
arch/arm/boot/dts/am571x-idk.dts
View File

@ -190,13 +190,13 @@
&cpsw_port1 {
phy-handle = <&ethphy0_sw>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
ti,dual-emac-pvid = <1>;
};
&cpsw_port2 {
phy-handle = <&ethphy1_sw>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
ti,dual-emac-pvid = <2>;
};

4
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
View File

@ -433,13 +433,13 @@
&cpsw_emac0 {
phy-handle = <&phy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
dual_emac_res_vlan = <2>;
};

4
arch/arm/boot/dts/am57xx-idk-common.dtsi
View File

@ -408,13 +408,13 @@
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy-handle = <&ethphy1>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
dual_emac_res_vlan = <2>;
};

6
arch/arm/boot/dts/bcm-hr2.dtsi
View File

@ -75,7 +75,7 @@
timer@20200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x20200 0x100>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
clocks = <&periph_clk>;
};
@ -83,7 +83,7 @@
compatible = "arm,cortex-a9-twd-timer";
reg = <0x20600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_HIGH)>;
IRQ_TYPE_EDGE_RISING)>;
clocks = <&periph_clk>;
};
@ -91,7 +91,7 @@
compatible = "arm,cortex-a9-twd-wdt";
reg = <0x20620 0x20>;
interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_HIGH)>;
IRQ_TYPE_EDGE_RISING)>;
clocks = <&periph_clk>;
};

2
arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
View File

@ -24,7 +24,7 @@
leds {
act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};

2
arch/arm/boot/dts/dm814x.dtsi
View File

@ -693,7 +693,7 @@
davinci_mdio: mdio@800 {
compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>;
clocks = <&cpsw_125mhz_gclk>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;

7
arch/arm/boot/dts/imx6q-b450v3.dts
View File

@ -65,13 +65,6 @@
};
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ldb {
status = "okay";

7
arch/arm/boot/dts/imx6q-b650v3.dts
View File

@ -65,13 +65,6 @@
};
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ldb {
status = "okay";

11
arch/arm/boot/dts/imx6q-b850v3.dts
View File

@ -53,17 +53,6 @@
};
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
};
&ldb {
fsl,dual-channel;
status = "okay";

15
arch/arm/boot/dts/imx6q-bx50v3.dtsi
View File

@ -377,3 +377,18 @@
#interrupt-cells = <1>;
};
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
};

12
arch/arm/boot/dts/mmp3-dell-ariel.dts
View File

@ -98,19 +98,19 @@
status = "okay";
};
&ssp3 {
&ssp1 {
status = "okay";
cs-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
firmware-flash@0 {
compatible = "st,m25p80", "jedec,spi-nor";
compatible = "winbond,w25q32", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-max-frequency = <104000000>;
m25p,fast-read;
};
};
&ssp4 {
cs-gpios = <&gpio 56 GPIO_ACTIVE_HIGH>;
&ssp2 {
cs-gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
status = "okay";
};

8
arch/arm/boot/dts/mmp3.dtsi
View File

@ -202,8 +202,7 @@
};
hsic_phy0: hsic-phy@f0001800 {
compatible = "marvell,mmp3-hsic-phy",
"usb-nop-xceiv";
compatible = "marvell,mmp3-hsic-phy";
reg = <0xf0001800 0x40>;
#phy-cells = <0>;
status = "disabled";
@ -224,8 +223,7 @@
};
hsic_phy1: hsic-phy@f0002800 {
compatible = "marvell,mmp3-hsic-phy",
"usb-nop-xceiv";
compatible = "marvell,mmp3-hsic-phy";
reg = <0xf0002800 0x40>;
#phy-cells = <0>;
status = "disabled";
@ -531,7 +529,7 @@
};
soc_clocks: clocks@d4050000 {
compatible = "marvell,mmp2-clock";
compatible = "marvell,mmp3-clock";
reg = <0xd4050000 0x1000>,
<0xd4282800 0x400>,
<0xd4015000 0x1000>;

4
arch/arm64/boot/dts/mediatek/mt8173.dtsi
View File

@ -1402,8 +1402,8 @@
"venc_lt_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
<&topckgen CLK_TOP_VENC_LT_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
<&topckgen CLK_TOP_UNIVPLL1_D2>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>,
<&topckgen CLK_TOP_VCODECPLL_370P5>;
};
jpegdec: jpegdec@18004000 {

4
drivers/soc/mediatek/mtk-cmdq-helper.c
View File

@ -351,7 +351,9 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb,
spin_unlock_irqrestore(&client->lock, flags);
}
mbox_send_message(client->chan, pkt);
err = mbox_send_message(client->chan, pkt);
if (err < 0)
return err;
/* We can send next packet immediately, so just call txdone. */
mbox_client_txdone(client->chan, 0);