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drm/i915/gvt: Revert "drm/i915/gvt: Refine the snapshort range of I915 MCHBAR to optimize gvt-g boot time"
This reverts commitf74a6d9a2c
. BXT needs to access 0x141000-0x1417ff register to obtain the dram info. But after the snapshot range of I915_MCHBAR is refined inf74a6d9a2c
, it only initializes the range of 0x144000-0x147fff for VGPU and then causes that the guest GPU can't get the initialized value for dram detection on BXT. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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@ -3303,7 +3303,7 @@ void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
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/* Special MMIO blocks. */
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static struct gvt_mmio_block mmio_blocks[] = {
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{D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
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{D_ALL, MCHBAR_MIRROR_REG_BASE, 0x4000, NULL, NULL},
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{D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
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{D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
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pvinfo_mmio_read, pvinfo_mmio_write},
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{D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
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@ -126,7 +126,4 @@
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#define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
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#define VF_GUARDBAND _MMIO(0x83a4)
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/* define the effective range of MCHBAR register on Sandybridge+ */
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#define MCHBAR_MIRROR_REG_BASE _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
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#endif
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