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clk: stm32f4: Add LSI & LSE clocks
This patch introduces the support of the LSI & LSE clocks. The clock drivers needs to disable the power domain write protection using syscon/regmap to enable these clocks. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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82a8e59e88
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@ -19,10 +19,14 @@
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#define STM32F4_RCC_PLLCFGR 0x04
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#define STM32F4_RCC_CFGR 0x08
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@ -31,6 +35,8 @@
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#define STM32F4_RCC_AHB3ENR 0x38
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#define STM32F4_RCC_APB1ENR 0x40
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#define STM32F4_RCC_APB2ENR 0x44
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#define STM32F4_RCC_BDCR 0x70
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#define STM32F4_RCC_CSR 0x74
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struct stm32f4_gate_data {
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u8 offset;
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@ -120,13 +126,12 @@ static const struct stm32f4_gate_data stm32f4_gates[] __initconst = {
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{ STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
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};
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enum { SYSTICK, FCLK, CLK_LSI, CLK_LSE, END_PRIMARY_CLK };
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/*
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* MAX_CLKS is the maximum value in the enumeration below plus the combined
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* hweight of stm32f42xx_gate_map (plus one).
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*/
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#define MAX_CLKS 74
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enum { SYSTICK, FCLK };
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#define MAX_CLKS (71 + END_PRIMARY_CLK + 1)
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/*
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* This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx
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@ -140,6 +145,8 @@ static struct clk_hw *clks[MAX_CLKS];
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static DEFINE_SPINLOCK(stm32f4_clk_lock);
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static void __iomem *base;
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static struct regmap *pdrm;
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/*
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* "Multiplier" device for APBx clocks.
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*
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@ -259,7 +266,7 @@ static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
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u64 table[ARRAY_SIZE(stm32f42xx_gate_map)];
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if (primary == 1) {
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if (WARN_ON(secondary > FCLK))
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if (WARN_ON(secondary >= END_PRIMARY_CLK))
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return -EINVAL;
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return secondary;
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}
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@ -276,7 +283,7 @@ static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
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table[BIT_ULL_WORD(secondary)] &=
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GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0);
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return FCLK + hweight64(table[0]) +
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return END_PRIMARY_CLK - 1 + hweight64(table[0]) +
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(BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) +
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(BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0);
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}
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@ -292,6 +299,98 @@ stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data)
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return clks[i];
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}
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#define to_rgclk(_rgate) container_of(_rgate, struct stm32_rgate, gate)
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static inline void disable_power_domain_write_protection(void)
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{
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if (pdrm)
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regmap_update_bits(pdrm, 0x00, (1 << 8), (1 << 8));
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}
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static inline void enable_power_domain_write_protection(void)
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{
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if (pdrm)
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regmap_update_bits(pdrm, 0x00, (1 << 8), (0 << 8));
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}
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struct stm32_rgate {
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struct clk_gate gate;
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u8 bit_rdy_idx;
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};
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#define RTC_TIMEOUT 1000000
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static int rgclk_enable(struct clk_hw *hw)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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struct stm32_rgate *rgate = to_rgclk(gate);
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u32 reg;
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int ret;
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disable_power_domain_write_protection();
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clk_gate_ops.enable(hw);
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ret = readl_relaxed_poll_timeout_atomic(gate->reg, reg,
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reg & rgate->bit_rdy_idx, 1000, RTC_TIMEOUT);
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enable_power_domain_write_protection();
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return ret;
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}
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static void rgclk_disable(struct clk_hw *hw)
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{
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clk_gate_ops.disable(hw);
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}
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static int rgclk_is_enabled(struct clk_hw *hw)
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{
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return clk_gate_ops.is_enabled(hw);
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}
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static const struct clk_ops rgclk_ops = {
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.enable = rgclk_enable,
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.disable = rgclk_disable,
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.is_enabled = rgclk_is_enabled,
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};
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static struct clk_hw *clk_register_rgate(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx,
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u8 clk_gate_flags, spinlock_t *lock)
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{
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struct stm32_rgate *rgate;
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struct clk_init_data init = { NULL };
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struct clk_hw *hw;
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int ret;
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rgate = kzalloc(sizeof(*rgate), GFP_KERNEL);
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if (!rgate)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &rgclk_ops;
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init.flags = flags;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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rgate->bit_rdy_idx = bit_rdy_idx;
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rgate->gate.lock = lock;
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rgate->gate.reg = reg;
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rgate->gate.bit_idx = bit_idx;
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rgate->gate.hw.init = &init;
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hw = &rgate->gate.hw;
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ret = clk_hw_register(dev, hw);
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if (ret) {
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kfree(rgate);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static const char *sys_parents[] __initdata = { "hsi", NULL, "pll" };
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static const struct clk_div_table ahb_div_table[] = {
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@ -319,6 +418,12 @@ static void __init stm32f4_rcc_init(struct device_node *np)
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return;
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}
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pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
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if (IS_ERR(pdrm)) {
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pdrm = NULL;
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pr_warn("%s: Unable to get syscfg\n", __func__);
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}
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hse_clk = of_clk_get_parent_name(np, 0);
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clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0,
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@ -371,6 +476,22 @@ static void __init stm32f4_rcc_init(struct device_node *np)
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}
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}
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clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,
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base + STM32F4_RCC_CSR, 0, 2, 0, &stm32f4_clk_lock);
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if (IS_ERR(clks[CLK_LSI])) {
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pr_err("Unable to register lsi clock\n");
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goto fail;
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}
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clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,
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base + STM32F4_RCC_BDCR, 0, 2, 0, &stm32f4_clk_lock);
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if (IS_ERR(clks[CLK_LSE])) {
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pr_err("Unable to register lse clock\n");
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goto fail;
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}
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of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
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return;
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fail:
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