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ARM: dts: omap5 clock data
This patch creates a unique node for each clock in the OMAP5 power, reset and clock manager (PRCM). Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -107,6 +107,58 @@
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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prm: prm@4ae06000 {
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compatible = "ti,omap5-prm";
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reg = <0x4ae06000 0x3000>;
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prm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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prm_clockdomains: clockdomains {
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};
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};
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cm_core_aon: cm_core_aon@4a004000 {
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compatible = "ti,omap5-cm-core-aon";
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reg = <0x4a004000 0x2000>;
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cm_core_aon_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cm_core_aon_clockdomains: clockdomains {
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};
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};
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scrm: scrm@4ae0a000 {
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compatible = "ti,omap5-scrm";
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reg = <0x4ae0a000 0x2000>;
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scrm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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scrm_clockdomains: clockdomains {
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};
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};
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cm_core: cm_core@4a008000 {
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compatible = "ti,omap5-cm-core";
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reg = <0x4a008000 0x3000>;
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cm_core_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cm_core_clockdomains: clockdomains {
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};
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};
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counter32k: counter@4ae04000 {
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compatible = "ti,omap-counter32k";
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reg = <0x4ae04000 0x40>;
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@ -739,3 +791,5 @@
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};
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};
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};
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/include/ "omap54xx-clocks.dtsi"
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1399
arch/arm/boot/dts/omap54xx-clocks.dtsi
Normal file
1399
arch/arm/boot/dts/omap54xx-clocks.dtsi
Normal file
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