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perf vendor events: Update Intel haswellx
Update to v25, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py to download and generate the latest events and metrics. Manually copy the haswellx files into perf and update mapfile.csv. Tested with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok 90: perf all metricgroups test : Ok 91: perf all metrics test : Failed 93: perf all PMU test : Ok The test 91 failure is a pre-existing failure on the test system with the metric Load_Miss_Real_Latency which is fixed by prefixing it with --metric-no-group. Signed-off-by: Ian Rogers <irogers@google.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.garry@huawei.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Kshipra Bopardikar <kshipra.bopardikar@intel.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sedat Dilek <sedat.dilek@gmail.com> Cc: Stephane Eranian <eranian@google.com> Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com> Link: http://lore.kernel.org/lkml/20220727220832.2865794-12-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers
Arnaldo Carvalho de Melo
parent
8e6389f931
commit
859fe0f4f2
@ -20,7 +20,7 @@
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"UMask": "0x2"
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},
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{
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"BriefDescription": "L1D miss oustandings duration in cycles",
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"BriefDescription": "L1D miss outstanding duration in cycles",
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"Counter": "2",
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"CounterHTOff": "2",
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"EventCode": "0x48",
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@ -592,7 +592,7 @@
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"UMask": "0x20"
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},
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{
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"BriefDescription": "All retired load uops.",
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"BriefDescription": "Retired load uops.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3",
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"Data_LA": "1",
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@ -600,11 +600,12 @@
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"EventCode": "0xD0",
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"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
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"PEBS": "1",
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"PublicDescription": "Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
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"SampleAfterValue": "2000003",
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"UMask": "0x81"
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},
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{
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"BriefDescription": "All retired store uops.",
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"BriefDescription": "Retired store uops.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3",
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"Data_LA": "1",
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@ -613,6 +614,7 @@
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"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
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"L1_Hit_Indication": "1",
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"PEBS": "1",
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"PublicDescription": "Counts all retired store uops.",
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"SampleAfterValue": "2000003",
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"UMask": "0x82"
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},
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@ -1071,7 +1073,6 @@
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xf4",
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"EventName": "SQ_MISC.SPLIT_LOCK",
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"PublicDescription": "SQ_MISC.SPLIT_LOCK",
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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}
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@ -111,17 +111,11 @@
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"MetricName": "CoreIPC_SMT"
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},
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{
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"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)",
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"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
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"MetricExpr": "( UOPS_EXECUTED.CORE / 2 / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@) ) if #SMT_on else UOPS_EXECUTED.CORE / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@)",
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"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
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"MetricName": "ILP"
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},
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{
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"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
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"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
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"MetricGroup": "Bad;BadSpec;BrMispredicts",
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"MetricName": "IpMispredict"
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},
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{
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"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
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"MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
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@ -170,6 +164,12 @@
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"MetricGroup": "Summary;TmaL1",
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"MetricName": "Instructions"
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},
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{
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"BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
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"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
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"MetricGroup": "Pipeline;Ret",
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"MetricName": "Retire"
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},
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{
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"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
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"MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
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@ -177,11 +177,16 @@
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"MetricName": "DSB_Coverage"
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},
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{
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"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)",
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"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
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"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
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"MetricGroup": "Bad;BadSpec;BrMispredicts",
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"MetricName": "IpMispredict"
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},
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{
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"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
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"MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )",
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"MetricGroup": "Mem;MemoryBound;MemoryLat",
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"MetricName": "Load_Miss_Real_Latency",
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"PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings."
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"MetricName": "Load_Miss_Real_Latency"
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},
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{
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"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
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@ -189,24 +194,6 @@
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"MetricGroup": "Mem;MemoryBound;MemoryBW",
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"MetricName": "MLP"
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},
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{
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"BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]",
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"MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L1D_Cache_Fill_BW"
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},
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{
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"BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]",
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"MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L2_Cache_Fill_BW"
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},
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{
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"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
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"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L3_Cache_Fill_BW"
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},
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{
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"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
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"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
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@ -238,6 +225,48 @@
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"MetricGroup": "Mem;MemoryTLB_SMT",
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"MetricName": "Page_Walks_Utilization_SMT"
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},
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{
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"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
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"MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L1D_Cache_Fill_BW"
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},
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{
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"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
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"MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L2_Cache_Fill_BW"
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},
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{
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"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
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"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L3_Cache_Fill_BW"
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},
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{
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"BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
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"MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L1D_Cache_Fill_BW_1T"
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},
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{
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"BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
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"MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L2_Cache_Fill_BW_1T"
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},
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{
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"BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
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"MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time)",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L3_Cache_Fill_BW_1T"
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},
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{
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"BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
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"MetricExpr": "0",
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"MetricGroup": "Mem;MemoryBW;Offcore",
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"MetricName": "L3_Cache_Access_BW_1T"
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},
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{
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"BriefDescription": "Average CPU Utilization",
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"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
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@ -1035,7 +1035,6 @@
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xA1",
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"EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
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"PublicDescription": "Cycles per core when uops are exectuted in port 0.",
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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},
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@ -1056,7 +1055,6 @@
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xA1",
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"EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
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"PublicDescription": "Cycles per core when uops are exectuted in port 1.",
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"SampleAfterValue": "2000003",
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"UMask": "0x2"
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},
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@ -1117,7 +1115,6 @@
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xA1",
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"EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
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"PublicDescription": "Cycles per core when uops are exectuted in port 4.",
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"SampleAfterValue": "2000003",
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"UMask": "0x10"
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},
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@ -1138,7 +1135,6 @@
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xA1",
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"EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
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"PublicDescription": "Cycles per core when uops are exectuted in port 5.",
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"SampleAfterValue": "2000003",
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"UMask": "0x20"
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},
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@ -1159,7 +1155,6 @@
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xA1",
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"EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
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"PublicDescription": "Cycles per core when uops are exectuted in port 6.",
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"SampleAfterValue": "2000003",
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"UMask": "0x40"
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},
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@ -511,7 +511,7 @@
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"Unit": "CBO"
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},
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{
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"BriefDescription": "AD",
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"BriefDescription": "UNC_C_RING_SINK_STARVED.AD",
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"Counter": "0,1,2,3",
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"EventCode": "0x6",
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"EventName": "UNC_C_RING_SINK_STARVED.AD",
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@ -520,7 +520,7 @@
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"Unit": "CBO"
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},
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{
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"BriefDescription": "AK",
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"BriefDescription": "UNC_C_RING_SINK_STARVED.AK",
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"Counter": "0,1,2,3",
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"EventCode": "0x6",
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"EventName": "UNC_C_RING_SINK_STARVED.AK",
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@ -529,7 +529,7 @@
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"Unit": "CBO"
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},
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{
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"BriefDescription": "IV",
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"BriefDescription": "UNC_C_RING_SINK_STARVED.IV",
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"Counter": "0,1,2,3",
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"EventCode": "0x6",
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"EventName": "UNC_C_RING_SINK_STARVED.IV",
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@ -538,7 +538,7 @@
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"Unit": "CBO"
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},
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{
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"BriefDescription": "BL",
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"BriefDescription": "UNC_C_RING_SINK_STARVED.BL",
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"Counter": "0,1,2,3",
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"EventCode": "0x6",
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"EventName": "UNC_C_RING_SINK_STARVED.BL",
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@ -9,7 +9,7 @@ GenuineIntel-6-96,v1.03,elkhartlake,core
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GenuineIntel-6-5[CF],v13,goldmont,core
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GenuineIntel-6-7A,v1.01,goldmontplus,core
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GenuineIntel-6-(3C|45|46),v31,haswell,core
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GenuineIntel-6-3F,v17,haswellx,core
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GenuineIntel-6-3F,v25,haswellx,core
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GenuineIntel-6-3A,v18,ivybridge,core
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GenuineIntel-6-3E,v19,ivytown,core
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GenuineIntel-6-2D,v20,jaketown,core
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