Merge branch 'pci/hotplug'

- Enable pciehp by default if USB4 is enabled because USB4/Thunderbolt
  tunneling depends on native PCIe hotplug (Albert Zhou)

- Make sure pciehp binds only to Downstream Ports, not Upstream Ports
  (Rafael J. Wysocki)

- Remove unused get_mode1_ECC_cap callback in shpchp (Ian Cowan)

- Enable pciehp Command Completed Interrupt only if supported to reduce
  confusion when looking at lspci output (Pali Rohár)

* pci/hotplug:
  PCI: pciehp: Enable Command Completed Interrupt only if supported
  PCI: shpchp: Remove unused get_mode1_ECC_cap callback
  PCI: acpiphp: Avoid setting is_hotplug_bridge for PCIe Upstream Ports
  PCI/portdrv: Set PCIE_PORT_SERVICE_HP for Root and Downstream Ports only
  PCI: pciehp: Enable by default if USB4 enabled
This commit is contained in:
Bjorn Helgaas 2022-12-10 10:36:32 -06:00
commit 84c3482963
8 changed files with 22 additions and 25 deletions

View File

@ -6,11 +6,14 @@
menuconfig HOTPLUG_PCI
bool "Support for PCI Hotplug"
depends on PCI && SYSFS
default y if USB4
help
Say Y here if you have a motherboard with a PCI Hotplug controller.
This allows you to add and remove PCI cards while the machine is
powered up and running.
Thunderbolt/USB4 PCIe tunneling depends on native PCIe hotplug.
When in doubt, say N.
if HOTPLUG_PCI

View File

@ -58,9 +58,6 @@ shpchp:
pciehp with commit 82a9e79ef132 ("PCI: pciehp: remove hpc_ops"). Clarify
if there was a specific reason not to apply the same change to shpchp.
* The ->get_mode1_ECC_cap callback in shpchp_hpc_ops is never invoked.
Why was it introduced? Can it be removed?
* The hardirq handler shpc_isr() queues events on a workqueue. It can be
simplified by converting it to threaded IRQ handling. Use pciehp as a
template.

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@ -411,6 +411,14 @@ static void check_hotplug_bridge(struct acpiphp_slot *slot, struct pci_dev *dev)
if (dev->is_hotplug_bridge)
return;
/*
* In the PCIe case, only Root Ports and Downstream Ports are capable of
* accommodating hotplug devices, so avoid marking Upstream Ports as
* "hotplug bridges".
*/
if (pci_is_pcie(dev) && pci_pcie_type(dev) == PCI_EXP_TYPE_UPSTREAM)
return;
list_for_each_entry(func, &slot->funcs, sibling) {
if (PCI_FUNC(dev->devfn) == func->function) {
dev->is_hotplug_bridge = 1;

View File

@ -811,7 +811,9 @@ static void pcie_enable_notification(struct controller *ctrl)
else
cmd |= PCI_EXP_SLTCTL_PDCE;
if (!pciehp_poll_mode)
cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
cmd |= PCI_EXP_SLTCTL_HPIE;
if (!pciehp_poll_mode && !NO_CMD_CMPL(ctrl))
cmd |= PCI_EXP_SLTCTL_CCIE;
mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
PCI_EXP_SLTCTL_PFDE |

View File

@ -311,7 +311,6 @@ struct hpc_ops {
int (*get_latch_status)(struct slot *slot, u8 *status);
int (*get_adapter_status)(struct slot *slot, u8 *status);
int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed);
int (*get_mode1_ECC_cap)(struct slot *slot, u8 *mode);
int (*get_prog_int)(struct slot *slot, u8 *prog_int);
int (*query_power_fault)(struct slot *slot);
void (*green_led_on)(struct slot *slot);

View File

@ -489,23 +489,6 @@ static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
return retval;
}
static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
{
int retval = 0;
struct controller *ctrl = slot->ctrl;
u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
if (pi == 2) {
*mode = (sec_bus_status & 0x0100) >> 8;
} else {
retval = -1;
}
ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode);
return retval;
}
static int hpc_query_power_fault(struct slot *slot)
{
struct controller *ctrl = slot->ctrl;
@ -900,7 +883,6 @@ static const struct hpc_ops shpchp_hpc_ops = {
.get_adapter_status = hpc_get_adapter_status,
.get_adapter_speed = hpc_get_adapter_speed,
.get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
.get_prog_int = hpc_get_prog_int,
.query_power_fault = hpc_query_power_fault,

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@ -4,6 +4,7 @@
#
config PCIEPORTBUS
bool "PCI Express Port Bus support"
default y if USB4
help
This enables PCI Express Port Bus support. Users can then enable
support for Native Hot-Plug, Advanced Error Reporting, Power
@ -15,9 +16,12 @@ config PCIEPORTBUS
config HOTPLUG_PCI_PCIE
bool "PCI Express Hotplug driver"
depends on HOTPLUG_PCI && PCIEPORTBUS
default y if USB4
help
Say Y here if you have a motherboard that supports PCI Express Native
Hotplug
Say Y here if you have a motherboard that supports PCIe native
hotplug.
Thunderbolt/USB4 PCIe tunneling depends on native PCIe hotplug.
When in doubt, say N.

View File

@ -209,6 +209,8 @@ static int get_port_device_capability(struct pci_dev *dev)
int services = 0;
if (dev->is_hotplug_bridge &&
(pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) &&
(pcie_ports_native || host->native_pcie_hotplug)) {
services |= PCIE_PORT_SERVICE_HP;