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arm, arm64: KVM: allow forced dcache flush on page faults
To allow handling of incoherent memslots in a subsequent patch, this patch adds a paramater 'ipa_uncached' to cache_coherent_guest_page() so that we can instruct it to flush the page's contents to DRAM even if the guest has caching globally enabled. Signed-off-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -161,9 +161,10 @@ static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
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}
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static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
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unsigned long size)
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unsigned long size,
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bool ipa_uncached)
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{
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if (!vcpu_has_cache_enabled(vcpu))
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if (!vcpu_has_cache_enabled(vcpu) || ipa_uncached)
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kvm_flush_dcache_to_poc((void *)hva, size);
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/*
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@ -852,6 +852,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
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struct vm_area_struct *vma;
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pfn_t pfn;
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pgprot_t mem_type = PAGE_S2;
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bool fault_ipa_uncached;
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write_fault = kvm_is_write_fault(vcpu);
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if (fault_status == FSC_PERM && !write_fault) {
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@ -918,6 +919,8 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
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if (!hugetlb && !force_pte)
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hugetlb = transparent_hugepage_adjust(&pfn, &fault_ipa);
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fault_ipa_uncached = false;
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if (hugetlb) {
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pmd_t new_pmd = pfn_pmd(pfn, mem_type);
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new_pmd = pmd_mkhuge(new_pmd);
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@ -925,7 +928,8 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
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kvm_set_s2pmd_writable(&new_pmd);
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kvm_set_pfn_dirty(pfn);
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}
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coherent_cache_guest_page(vcpu, hva & PMD_MASK, PMD_SIZE);
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coherent_cache_guest_page(vcpu, hva & PMD_MASK, PMD_SIZE,
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fault_ipa_uncached);
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ret = stage2_set_pmd_huge(kvm, memcache, fault_ipa, &new_pmd);
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} else {
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pte_t new_pte = pfn_pte(pfn, mem_type);
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@ -933,7 +937,8 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
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kvm_set_s2pte_writable(&new_pte);
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kvm_set_pfn_dirty(pfn);
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}
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coherent_cache_guest_page(vcpu, hva, PAGE_SIZE);
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coherent_cache_guest_page(vcpu, hva, PAGE_SIZE,
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fault_ipa_uncached);
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ret = stage2_set_pte(kvm, memcache, fault_ipa, &new_pte,
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pgprot_val(mem_type) == pgprot_val(PAGE_S2_DEVICE));
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}
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@ -243,9 +243,10 @@ static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
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}
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static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
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unsigned long size)
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unsigned long size,
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bool ipa_uncached)
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{
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if (!vcpu_has_cache_enabled(vcpu))
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if (!vcpu_has_cache_enabled(vcpu) || ipa_uncached)
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kvm_flush_dcache_to_poc((void *)hva, size);
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if (!icache_is_aliasing()) { /* PIPT */
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