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mtd: rawnand: Deprecate ->dev_ready() and ->waitfunc()
Those hooks have been replaced by ->exec_op(). Move them to the nand_legacy struct. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
parent
bf6065c6c0
commit
8395b753d7
@ -197,7 +197,7 @@ to read back the state of the pin. The function has no arguments and
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should return 0, if the device is busy (R/B pin is low) and 1, if the
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device is ready (R/B pin is high). If the hardware interface does not
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give access to the ready busy pin, then the function must not be defined
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and the function pointer this->dev_ready is set to NULL.
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and the function pointer this->legacy.dev_ready is set to NULL.
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Init function
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-------------
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@ -242,7 +242,7 @@ necessary information about the device.
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/* Set command delay time, see datasheet for correct value */
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this->chip_delay = CHIP_DEPENDEND_COMMAND_DELAY;
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/* Assign the device ready function, if available */
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this->dev_ready = board_dev_ready;
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this->legacy.dev_ready = board_dev_ready;
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this->eccmode = NAND_ECC_SOFT;
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/* Scan to find existence of the device */
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@ -215,9 +215,9 @@ static int ams_delta_init(struct platform_device *pdev)
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this->legacy.read_buf = ams_delta_read_buf;
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this->legacy.cmd_ctrl = ams_delta_hwcontrol;
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if (gpio_request(AMS_DELTA_GPIO_PIN_NAND_RB, "nand_rdy") == 0) {
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this->dev_ready = ams_delta_nand_ready;
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this->legacy.dev_ready = ams_delta_nand_ready;
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} else {
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this->dev_ready = NULL;
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this->legacy.dev_ready = NULL;
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pr_notice("Couldn't request gpio for Delta NAND ready.\n");
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}
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/* 25 us command delay time */
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@ -488,14 +488,14 @@ static void atmel_nand_select_chip(struct nand_chip *chip, int cs)
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if (cs < 0 || cs >= nand->numcs) {
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nand->activecs = NULL;
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chip->dev_ready = NULL;
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chip->legacy.dev_ready = NULL;
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return;
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}
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nand->activecs = &nand->cs[cs];
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if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
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chip->dev_ready = atmel_nand_dev_ready;
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chip->legacy.dev_ready = atmel_nand_dev_ready;
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}
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static int atmel_hsmc_nand_dev_ready(struct nand_chip *chip)
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@ -528,7 +528,7 @@ static void atmel_hsmc_nand_select_chip(struct nand_chip *chip, int cs)
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}
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if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
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chip->dev_ready = atmel_hsmc_nand_dev_ready;
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chip->legacy.dev_ready = atmel_hsmc_nand_dev_ready;
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regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
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ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
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@ -945,7 +945,7 @@ static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
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dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
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ret);
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status = chip->waitfunc(chip);
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status = chip->legacy.waitfunc(chip);
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if (status & NAND_STATUS_FAIL)
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return -EIO;
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@ -342,7 +342,8 @@ static void au1550_command(struct nand_chip *this, unsigned command,
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/* Apply a short delay always to ensure that we do wait tWB. */
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ndelay(100);
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/* Wait for a chip to become ready... */
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for (i = this->chip_delay; !this->dev_ready(this) && i > 0; --i)
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for (i = this->chip_delay;
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!this->legacy.dev_ready(this) && i > 0; --i)
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udelay(1);
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/* Release -CE and re-enable interrupts. */
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@ -353,7 +354,7 @@ static void au1550_command(struct nand_chip *this, unsigned command,
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/* Apply this short delay always to ensure that we do wait tWB. */
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ndelay(100);
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while(!this->dev_ready(this));
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while(!this->legacy.dev_ready(this));
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}
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static int find_nand_cs(unsigned long nand_base)
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@ -428,7 +429,7 @@ static int au1550nd_probe(struct platform_device *pdev)
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}
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ctx->cs = cs;
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this->dev_ready = au1550_device_ready;
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this->legacy.dev_ready = au1550_device_ready;
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this->select_chip = au1550_select_chip;
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this->legacy.cmdfunc = au1550_command;
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@ -385,7 +385,7 @@ int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
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b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
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nand_chip->legacy.cmd_ctrl = bcm47xxnflash_ops_bcm4706_cmd_ctrl;
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nand_chip->dev_ready = bcm47xxnflash_ops_bcm4706_dev_ready;
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nand_chip->legacy.dev_ready = bcm47xxnflash_ops_bcm4706_dev_ready;
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b47n->nand_chip.legacy.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc;
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b47n->nand_chip.legacy.read_byte = bcm47xxnflash_ops_bcm4706_read_byte;
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b47n->nand_chip.legacy.read_buf = bcm47xxnflash_ops_bcm4706_read_buf;
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@ -2272,7 +2272,7 @@ static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
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chip->legacy.cmd_ctrl = brcmnand_cmd_ctrl;
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chip->legacy.cmdfunc = brcmnand_cmdfunc;
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chip->waitfunc = brcmnand_waitfunc;
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chip->legacy.waitfunc = brcmnand_waitfunc;
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chip->legacy.read_byte = brcmnand_read_byte;
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chip->legacy.read_buf = brcmnand_read_buf;
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chip->legacy.write_buf = brcmnand_write_buf;
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@ -704,7 +704,7 @@ static int cafe_nand_probe(struct pci_dev *pdev,
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}
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cafe->nand.legacy.cmdfunc = cafe_nand_cmdfunc;
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cafe->nand.dev_ready = cafe_device_ready;
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cafe->nand.legacy.dev_ready = cafe_device_ready;
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cafe->nand.legacy.read_byte = cafe_read_byte;
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cafe->nand.legacy.read_buf = cafe_read_buf;
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cafe->nand.legacy.write_buf = cafe_write_buf;
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@ -176,7 +176,7 @@ static int __init cmx270_init(void)
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this->legacy.IO_ADDR_R = cmx270_nand_io;
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this->legacy.IO_ADDR_W = cmx270_nand_io;
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this->legacy.cmd_ctrl = cmx270_hwcontrol;
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this->dev_ready = cmx270_device_ready;
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this->legacy.dev_ready = cmx270_device_ready;
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/* 15 us command delay time */
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this->chip_delay = 20;
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@ -207,7 +207,7 @@ static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
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}
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this->legacy.cmd_ctrl = cs553x_hwcontrol;
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this->dev_ready = cs553x_device_ready;
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this->legacy.dev_ready = cs553x_device_ready;
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this->legacy.read_byte = cs553x_read_byte;
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this->legacy.read_buf = cs553x_read_buf;
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this->legacy.write_buf = cs553x_write_buf;
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@ -782,7 +782,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
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/* Set address of hardware control function */
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info->chip.legacy.cmd_ctrl = nand_davinci_hwcontrol;
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info->chip.dev_ready = nand_davinci_dev_ready;
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info->chip.legacy.dev_ready = nand_davinci_dev_ready;
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/* Speed up buffer I/O */
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info->chip.legacy.read_buf = nand_davinci_read_buf;
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@ -287,7 +287,8 @@ static void denali_cmd_ctrl(struct nand_chip *chip, int dat, unsigned int ctrl)
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return;
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/*
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* Some commands are followed by chip->dev_ready or chip->waitfunc.
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* Some commands are followed by chip->legacy.dev_ready or
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* chip->legacy.waitfunc.
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* irq_status must be cleared here to catch the R/B# interrupt later.
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*/
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if (ctrl & NAND_CTRL_CHANGE)
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@ -1346,8 +1347,8 @@ int denali_init(struct denali_nand_info *denali)
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chip->legacy.read_byte = denali_read_byte;
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chip->legacy.write_byte = denali_write_byte;
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chip->legacy.cmd_ctrl = denali_cmd_ctrl;
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chip->dev_ready = denali_dev_ready;
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chip->waitfunc = denali_waitfunc;
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chip->legacy.dev_ready = denali_dev_ready;
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chip->legacy.waitfunc = denali_waitfunc;
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if (features & FEATURES__INDEX_ADDR) {
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denali->host_read = denali_indexed_read;
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@ -715,7 +715,7 @@ static void doc2001plus_command(struct nand_chip *this, unsigned command,
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return;
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case NAND_CMD_RESET:
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if (this->dev_ready)
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if (this->legacy.dev_ready)
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break;
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udelay(this->chip_delay);
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WriteDOC(NAND_CMD_STATUS, docptr, Mplus_FlashCmd);
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@ -730,7 +730,7 @@ static void doc2001plus_command(struct nand_chip *this, unsigned command,
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* If we don't have access to the busy pin, we apply the given
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* command delay
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*/
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if (!this->dev_ready) {
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if (!this->legacy.dev_ready) {
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udelay(this->chip_delay);
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return;
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}
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@ -740,7 +740,7 @@ static void doc2001plus_command(struct nand_chip *this, unsigned command,
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* any case on any machine. */
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ndelay(100);
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/* wait until command is processed */
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while (!this->dev_ready(this)) ;
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while (!this->legacy.dev_ready(this)) ;
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}
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static int doc200x_dev_ready(struct nand_chip *this)
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@ -1570,8 +1570,8 @@ static int __init doc_probe(unsigned long physadr)
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nand_set_controller_data(nand, doc);
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nand->select_chip = doc200x_select_chip;
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nand->legacy.cmd_ctrl = doc200x_hwcontrol;
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nand->dev_ready = doc200x_dev_ready;
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nand->waitfunc = doc200x_wait;
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nand->legacy.dev_ready = doc200x_dev_ready;
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nand->legacy.waitfunc = doc200x_wait;
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nand->block_bad = doc200x_block_bad;
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nand->ecc.hwctl = doc200x_enable_hwecc;
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nand->ecc.calculate = doc200x_calculate_ecc;
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@ -781,7 +781,7 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
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chip->legacy.read_buf = fsl_elbc_read_buf;
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chip->select_chip = fsl_elbc_select_chip;
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chip->legacy.cmdfunc = fsl_elbc_cmdfunc;
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chip->waitfunc = fsl_elbc_wait;
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chip->legacy.waitfunc = fsl_elbc_wait;
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chip->set_features = nand_get_set_features_notsupp;
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chip->get_features = nand_get_set_features_notsupp;
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@ -866,7 +866,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
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chip->legacy.read_buf = fsl_ifc_read_buf;
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chip->select_chip = fsl_ifc_select_chip;
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chip->legacy.cmdfunc = fsl_ifc_cmdfunc;
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chip->waitfunc = fsl_ifc_wait;
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chip->legacy.waitfunc = fsl_ifc_wait;
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chip->set_features = nand_get_set_features_notsupp;
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chip->get_features = nand_get_set_features_notsupp;
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@ -173,7 +173,7 @@ static int fun_chip_init(struct fsl_upm_nand *fun,
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fun->chip.select_chip = fun_select_chip;
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if (fun->rnb_gpio[0] >= 0)
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fun->chip.dev_ready = fun_chip_ready;
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fun->chip.legacy.dev_ready = fun_chip_ready;
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mtd->dev.parent = fun->dev;
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@ -271,7 +271,7 @@ static int gpio_nand_probe(struct platform_device *pdev)
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}
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/* Using RDY pin */
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if (gpiomtd->rdy)
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chip->dev_ready = gpio_nand_devready;
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chip->legacy.dev_ready = gpio_nand_devready;
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nand_set_flash_node(chip, pdev->dev.of_node);
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chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R;
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@ -1903,7 +1903,7 @@ static int gpmi_nand_init(struct gpmi_nand_data *this)
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chip->select_chip = gpmi_select_chip;
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chip->setup_data_interface = gpmi_setup_data_interface;
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chip->legacy.cmd_ctrl = gpmi_cmd_ctrl;
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chip->dev_ready = gpmi_dev_ready;
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chip->legacy.dev_ready = gpmi_dev_ready;
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chip->legacy.read_byte = gpmi_read_byte;
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chip->legacy.read_buf = gpmi_read_buf;
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chip->legacy.write_buf = gpmi_write_buf;
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@ -431,7 +431,7 @@ static int jz_nand_probe(struct platform_device *pdev)
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chip->dummy_controller.ops = &jz_nand_controller_ops;
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if (nand->busy_gpio)
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chip->dev_ready = jz_nand_dev_ready;
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chip->legacy.dev_ready = jz_nand_dev_ready;
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platform_set_drvdata(pdev, nand);
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@ -256,7 +256,7 @@ static int jz4780_nand_init_chip(struct platform_device *pdev,
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dev_err(dev, "failed to request busy GPIO: %d\n", ret);
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return ret;
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} else if (nand->busy_gpio) {
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nand->chip.dev_ready = jz4780_nand_dev_ready;
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nand->chip.legacy.dev_ready = jz4780_nand_dev_ready;
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}
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nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
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@ -740,7 +740,7 @@ static int lpc32xx_nand_probe(struct platform_device *pdev)
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goto put_clk;
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nand_chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl;
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nand_chip->dev_ready = lpc32xx_nand_device_ready;
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nand_chip->legacy.dev_ready = lpc32xx_nand_device_ready;
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nand_chip->chip_delay = 25; /* us */
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nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base);
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nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base);
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@ -760,7 +760,7 @@ static int lpc32xx_nand_probe(struct platform_device *pdev)
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nand_chip->ecc.read_oob = lpc32xx_read_oob;
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nand_chip->ecc.strength = 4;
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nand_chip->ecc.bytes = 10;
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nand_chip->waitfunc = lpc32xx_waitfunc;
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nand_chip->legacy.waitfunc = lpc32xx_waitfunc;
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nand_chip->options = NAND_NO_SUBPAGE_WRITE;
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nand_chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
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@ -881,7 +881,7 @@ static int lpc32xx_nand_probe(struct platform_device *pdev)
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chip->legacy.IO_ADDR_R = SLC_DATA(host->io_base);
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chip->legacy.IO_ADDR_W = SLC_DATA(host->io_base);
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chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl;
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chip->dev_ready = lpc32xx_nand_device_ready;
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chip->legacy.dev_ready = lpc32xx_nand_device_ready;
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chip->chip_delay = 20; /* 20us command delay time */
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/* Init NAND controller */
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@ -692,7 +692,7 @@ static int mpc5121_nfc_probe(struct platform_device *op)
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}
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mtd->name = "MPC5121 NAND";
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chip->dev_ready = mpc5121_nfc_dev_ready;
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chip->legacy.dev_ready = mpc5121_nfc_dev_ready;
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chip->legacy.cmdfunc = mpc5121_nfc_command;
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chip->legacy.read_byte = mpc5121_nfc_read_byte;
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chip->legacy.read_buf = mpc5121_nfc_read_buf;
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@ -1332,7 +1332,7 @@ static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc,
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nand_set_controller_data(nand, nfc);
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nand->options |= NAND_USE_BOUNCE_BUFFER | NAND_SUBPAGE_READ;
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nand->dev_ready = mtk_nfc_dev_ready;
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nand->legacy.dev_ready = mtk_nfc_dev_ready;
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nand->select_chip = mtk_nfc_select_chip;
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nand->legacy.write_byte = mtk_nfc_write_byte;
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nand->legacy.write_buf = mtk_nfc_write_buf;
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@ -1773,7 +1773,7 @@ static int mxcnd_probe(struct platform_device *pdev)
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nand_set_controller_data(this, host);
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nand_set_flash_node(this, pdev->dev.of_node),
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this->dev_ready = mxc_nand_dev_ready;
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this->legacy.dev_ready = mxc_nand_dev_ready;
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this->legacy.cmdfunc = mxc_nand_command;
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this->legacy.read_byte = mxc_nand_read_byte;
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this->legacy.write_buf = mxc_nand_write_buf;
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@ -604,7 +604,7 @@ static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
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/* Wait for the device to get ready */
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for (i = 0; i < timeo; i++) {
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if (chip->dev_ready(chip))
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if (chip->legacy.dev_ready(chip))
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break;
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touch_softlockup_watchdog();
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mdelay(1);
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@ -628,12 +628,12 @@ void nand_wait_ready(struct nand_chip *chip)
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/* Wait until command is processed or timeout occurs */
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timeo = jiffies + msecs_to_jiffies(timeo);
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do {
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if (chip->dev_ready(chip))
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if (chip->legacy.dev_ready(chip))
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return;
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cond_resched();
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} while (time_before(jiffies, timeo));
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if (!chip->dev_ready(chip))
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if (!chip->legacy.dev_ready(chip))
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pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
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}
|
||||
EXPORT_SYMBOL_GPL(nand_wait_ready);
|
||||
@ -804,7 +804,7 @@ static void nand_command(struct nand_chip *chip, unsigned int command,
|
||||
return;
|
||||
|
||||
case NAND_CMD_RESET:
|
||||
if (chip->dev_ready)
|
||||
if (chip->legacy.dev_ready)
|
||||
break;
|
||||
udelay(chip->chip_delay);
|
||||
chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS,
|
||||
@ -831,7 +831,7 @@ static void nand_command(struct nand_chip *chip, unsigned int command,
|
||||
* If we don't have access to the busy pin, we apply the given
|
||||
* command delay
|
||||
*/
|
||||
if (!chip->dev_ready) {
|
||||
if (!chip->legacy.dev_ready) {
|
||||
udelay(chip->chip_delay);
|
||||
return;
|
||||
}
|
||||
@ -941,7 +941,7 @@ static void nand_command_lp(struct nand_chip *chip, unsigned int command,
|
||||
return;
|
||||
|
||||
case NAND_CMD_RESET:
|
||||
if (chip->dev_ready)
|
||||
if (chip->legacy.dev_ready)
|
||||
break;
|
||||
udelay(chip->chip_delay);
|
||||
chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS,
|
||||
@ -983,7 +983,7 @@ static void nand_command_lp(struct nand_chip *chip, unsigned int command,
|
||||
* If we don't have access to the busy pin, we apply the given
|
||||
* command delay.
|
||||
*/
|
||||
if (!chip->dev_ready) {
|
||||
if (!chip->legacy.dev_ready) {
|
||||
udelay(chip->chip_delay);
|
||||
return;
|
||||
}
|
||||
@ -1069,8 +1069,8 @@ static void panic_nand_wait(struct nand_chip *chip, unsigned long timeo)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < timeo; i++) {
|
||||
if (chip->dev_ready) {
|
||||
if (chip->dev_ready(chip))
|
||||
if (chip->legacy.dev_ready) {
|
||||
if (chip->legacy.dev_ready(chip))
|
||||
break;
|
||||
} else {
|
||||
int ret;
|
||||
@ -1117,8 +1117,8 @@ static int nand_wait(struct nand_chip *chip)
|
||||
else {
|
||||
timeo = jiffies + msecs_to_jiffies(timeo);
|
||||
do {
|
||||
if (chip->dev_ready) {
|
||||
if (chip->dev_ready(chip))
|
||||
if (chip->legacy.dev_ready) {
|
||||
if (chip->legacy.dev_ready(chip))
|
||||
break;
|
||||
} else {
|
||||
ret = nand_read_data_op(chip, &status,
|
||||
@ -1827,7 +1827,7 @@ int nand_prog_page_end_op(struct nand_chip *chip)
|
||||
return ret;
|
||||
} else {
|
||||
chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
|
||||
ret = chip->waitfunc(chip);
|
||||
ret = chip->legacy.waitfunc(chip);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
@ -1875,7 +1875,7 @@ int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
|
||||
page);
|
||||
chip->legacy.write_buf(chip, buf, len);
|
||||
chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
|
||||
status = chip->waitfunc(chip);
|
||||
status = chip->legacy.waitfunc(chip);
|
||||
}
|
||||
|
||||
if (status & NAND_STATUS_FAIL)
|
||||
@ -2106,7 +2106,7 @@ int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)
|
||||
chip->legacy.cmdfunc(chip, NAND_CMD_ERASE1, -1, page);
|
||||
chip->legacy.cmdfunc(chip, NAND_CMD_ERASE2, -1, -1);
|
||||
|
||||
ret = chip->waitfunc(chip);
|
||||
ret = chip->legacy.waitfunc(chip);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
@ -2157,7 +2157,7 @@ static int nand_set_features_op(struct nand_chip *chip, u8 feature,
|
||||
for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
|
||||
chip->legacy.write_byte(chip, params[i]);
|
||||
|
||||
ret = chip->waitfunc(chip);
|
||||
ret = chip->legacy.waitfunc(chip);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
@ -2222,7 +2222,7 @@ static int nand_wait_rdy_op(struct nand_chip *chip, unsigned int timeout_ms,
|
||||
}
|
||||
|
||||
/* Apply delay or wait for ready/busy pin */
|
||||
if (!chip->dev_ready)
|
||||
if (!chip->legacy.dev_ready)
|
||||
udelay(chip->chip_delay);
|
||||
else
|
||||
nand_wait_ready(chip);
|
||||
@ -4927,8 +4927,8 @@ static void nand_set_defaults(struct nand_chip *chip)
|
||||
chip->legacy.cmdfunc = nand_command;
|
||||
|
||||
/* check, if a user supplied wait function given */
|
||||
if (chip->waitfunc == NULL)
|
||||
chip->waitfunc = nand_wait;
|
||||
if (chip->legacy.waitfunc == NULL)
|
||||
chip->legacy.waitfunc = nand_wait;
|
||||
|
||||
if (!chip->select_chip)
|
||||
chip->select_chip = nand_select_chip;
|
||||
|
@ -2251,7 +2251,7 @@ static int __init ns_init_module(void)
|
||||
*/
|
||||
chip->legacy.cmd_ctrl = ns_hwcontrol;
|
||||
chip->legacy.read_byte = ns_nand_read_byte;
|
||||
chip->dev_ready = ns_device_ready;
|
||||
chip->legacy.dev_ready = ns_device_ready;
|
||||
chip->legacy.write_buf = ns_nand_write_buf;
|
||||
chip->legacy.read_buf = ns_nand_read_buf;
|
||||
chip->ecc.mode = NAND_ECC_SOFT;
|
||||
|
@ -145,7 +145,7 @@ static int ndfc_chip_init(struct ndfc_controller *ndfc,
|
||||
chip->legacy.IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
|
||||
chip->legacy.IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
|
||||
chip->legacy.cmd_ctrl = ndfc_hwcontrol;
|
||||
chip->dev_ready = ndfc_ready;
|
||||
chip->legacy.dev_ready = ndfc_ready;
|
||||
chip->select_chip = ndfc_select_chip;
|
||||
chip->chip_delay = 50;
|
||||
chip->controller = &ndfc->ndfc_control;
|
||||
|
@ -175,7 +175,7 @@ static void nuc900_nand_command_lp(struct nand_chip *chip,
|
||||
return;
|
||||
|
||||
case NAND_CMD_RESET:
|
||||
if (chip->dev_ready)
|
||||
if (chip->legacy.dev_ready)
|
||||
break;
|
||||
udelay(chip->chip_delay);
|
||||
|
||||
@ -196,7 +196,7 @@ static void nuc900_nand_command_lp(struct nand_chip *chip,
|
||||
write_cmd_reg(nand, NAND_CMD_READSTART);
|
||||
default:
|
||||
|
||||
if (!chip->dev_ready) {
|
||||
if (!chip->legacy.dev_ready) {
|
||||
udelay(chip->chip_delay);
|
||||
return;
|
||||
}
|
||||
@ -206,7 +206,7 @@ static void nuc900_nand_command_lp(struct nand_chip *chip,
|
||||
* any case on any machine. */
|
||||
ndelay(100);
|
||||
|
||||
while (!chip->dev_ready(chip))
|
||||
while (!chip->legacy.dev_ready(chip))
|
||||
;
|
||||
}
|
||||
|
||||
@ -255,7 +255,7 @@ static int nuc900_nand_probe(struct platform_device *pdev)
|
||||
clk_enable(nuc900_nand->clk);
|
||||
|
||||
chip->legacy.cmdfunc = nuc900_nand_command_lp;
|
||||
chip->dev_ready = nuc900_nand_devready;
|
||||
chip->legacy.dev_ready = nuc900_nand_devready;
|
||||
chip->legacy.read_byte = nuc900_nand_read_byte;
|
||||
chip->legacy.write_buf = nuc900_nand_write_buf;
|
||||
chip->legacy.read_buf = nuc900_nand_read_buf;
|
||||
|
@ -2247,10 +2247,10 @@ static int omap_nand_probe(struct platform_device *pdev)
|
||||
* device and read status register until you get a failure or success
|
||||
*/
|
||||
if (info->ready_gpiod) {
|
||||
nand_chip->dev_ready = omap_dev_ready;
|
||||
nand_chip->legacy.dev_ready = omap_dev_ready;
|
||||
nand_chip->chip_delay = 0;
|
||||
} else {
|
||||
nand_chip->waitfunc = omap_wait;
|
||||
nand_chip->legacy.waitfunc = omap_wait;
|
||||
nand_chip->chip_delay = 50;
|
||||
}
|
||||
|
||||
|
@ -140,7 +140,7 @@ static int pasemi_nand_probe(struct platform_device *ofdev)
|
||||
}
|
||||
|
||||
chip->legacy.cmd_ctrl = pasemi_hwcontrol;
|
||||
chip->dev_ready = pasemi_device_ready;
|
||||
chip->legacy.dev_ready = pasemi_device_ready;
|
||||
chip->legacy.read_buf = pasemi_read_buf;
|
||||
chip->legacy.write_buf = pasemi_write_buf;
|
||||
chip->chip_delay = 0;
|
||||
|
@ -63,7 +63,7 @@ static int plat_nand_probe(struct platform_device *pdev)
|
||||
data->chip.legacy.IO_ADDR_R = data->io_base;
|
||||
data->chip.legacy.IO_ADDR_W = data->io_base;
|
||||
data->chip.legacy.cmd_ctrl = pdata->ctrl.cmd_ctrl;
|
||||
data->chip.dev_ready = pdata->ctrl.dev_ready;
|
||||
data->chip.legacy.dev_ready = pdata->ctrl.dev_ready;
|
||||
data->chip.select_chip = pdata->ctrl.select_chip;
|
||||
data->chip.legacy.write_buf = pdata->ctrl.write_buf;
|
||||
data->chip.legacy.read_buf = pdata->ctrl.read_buf;
|
||||
|
@ -373,7 +373,7 @@ static int r852_wait(struct nand_chip *chip)
|
||||
msecs_to_jiffies(400) : msecs_to_jiffies(20));
|
||||
|
||||
while (time_before(jiffies, timeout))
|
||||
if (chip->dev_ready(chip))
|
||||
if (chip->legacy.dev_ready(chip))
|
||||
break;
|
||||
|
||||
nand_status_op(chip, &status);
|
||||
@ -854,8 +854,8 @@ static int r852_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
|
||||
|
||||
/* commands */
|
||||
chip->legacy.cmd_ctrl = r852_cmdctl;
|
||||
chip->waitfunc = r852_wait;
|
||||
chip->dev_ready = r852_ready;
|
||||
chip->legacy.waitfunc = r852_wait;
|
||||
chip->legacy.dev_ready = r852_ready;
|
||||
|
||||
/* I/O */
|
||||
chip->legacy.read_byte = r852_read_byte;
|
||||
|
@ -885,7 +885,7 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
|
||||
info->sel_reg = regs + S3C2410_NFCONF;
|
||||
info->sel_bit = S3C2410_NFCONF_nFCE;
|
||||
chip->legacy.cmd_ctrl = s3c2410_nand_hwcontrol;
|
||||
chip->dev_ready = s3c2410_nand_devready;
|
||||
chip->legacy.dev_ready = s3c2410_nand_devready;
|
||||
break;
|
||||
|
||||
case TYPE_S3C2440:
|
||||
@ -893,7 +893,7 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
|
||||
info->sel_reg = regs + S3C2440_NFCONT;
|
||||
info->sel_bit = S3C2440_NFCONT_nFCE;
|
||||
chip->legacy.cmd_ctrl = s3c2440_nand_hwcontrol;
|
||||
chip->dev_ready = s3c2440_nand_devready;
|
||||
chip->legacy.dev_ready = s3c2440_nand_devready;
|
||||
chip->legacy.read_buf = s3c2440_nand_read_buf;
|
||||
chip->legacy.write_buf = s3c2440_nand_write_buf;
|
||||
break;
|
||||
@ -903,7 +903,7 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
|
||||
info->sel_reg = regs + S3C2440_NFCONT;
|
||||
info->sel_bit = S3C2412_NFCONT_nFCE0;
|
||||
chip->legacy.cmd_ctrl = s3c2440_nand_hwcontrol;
|
||||
chip->dev_ready = s3c2412_nand_devready;
|
||||
chip->legacy.dev_ready = s3c2412_nand_devready;
|
||||
|
||||
if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
|
||||
dev_info(info->device, "System booted from NAND\n");
|
||||
|
@ -157,7 +157,7 @@ static int sharpsl_nand_probe(struct platform_device *pdev)
|
||||
this->legacy.IO_ADDR_W = sharpsl->io + FLASHIO;
|
||||
/* Set address of hardware control function */
|
||||
this->legacy.cmd_ctrl = sharpsl_nand_hwcontrol;
|
||||
this->dev_ready = sharpsl_nand_dev_ready;
|
||||
this->legacy.dev_ready = sharpsl_nand_dev_ready;
|
||||
/* 15 us command delay time */
|
||||
this->chip_delay = 15;
|
||||
/* set eccmode using hardware ECC */
|
||||
|
@ -156,7 +156,7 @@ static int socrates_nand_probe(struct platform_device *ofdev)
|
||||
nand_chip->legacy.read_byte = socrates_nand_read_byte;
|
||||
nand_chip->legacy.write_buf = socrates_nand_write_buf;
|
||||
nand_chip->legacy.read_buf = socrates_nand_read_buf;
|
||||
nand_chip->dev_ready = socrates_nand_device_ready;
|
||||
nand_chip->legacy.dev_ready = socrates_nand_device_ready;
|
||||
|
||||
nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
|
||||
nand_chip->ecc.algo = NAND_ECC_HAMMING;
|
||||
|
@ -442,9 +442,9 @@ static void sunxi_nfc_select_chip(struct nand_chip *nand, int chip)
|
||||
ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
|
||||
NFC_PAGE_SHIFT(nand->page_shift);
|
||||
if (sel->rb < 0) {
|
||||
nand->dev_ready = NULL;
|
||||
nand->legacy.dev_ready = NULL;
|
||||
} else {
|
||||
nand->dev_ready = sunxi_nfc_dev_ready;
|
||||
nand->legacy.dev_ready = sunxi_nfc_dev_ready;
|
||||
ctl |= NFC_RB_SEL(sel->rb);
|
||||
}
|
||||
|
||||
|
@ -314,7 +314,7 @@ static int tango_write_page(struct nand_chip *chip, const u8 *buf,
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
status = chip->waitfunc(chip);
|
||||
status = chip->legacy.waitfunc(chip);
|
||||
if (status & NAND_STATUS_FAIL)
|
||||
return -EIO;
|
||||
|
||||
@ -569,7 +569,7 @@ static int chip_init(struct device *dev, struct device_node *np)
|
||||
chip->legacy.read_buf = tango_read_buf;
|
||||
chip->select_chip = tango_select_chip;
|
||||
chip->legacy.cmd_ctrl = tango_cmd_ctrl;
|
||||
chip->dev_ready = tango_dev_ready;
|
||||
chip->legacy.dev_ready = tango_dev_ready;
|
||||
chip->setup_data_interface = tango_set_timings;
|
||||
chip->options = NAND_USE_BOUNCE_BUFFER |
|
||||
NAND_NO_SUBPAGE_WRITE |
|
||||
|
@ -404,7 +404,7 @@ static int tmio_probe(struct platform_device *dev)
|
||||
|
||||
/* Set address of hardware control function */
|
||||
nand_chip->legacy.cmd_ctrl = tmio_nand_hwcontrol;
|
||||
nand_chip->dev_ready = tmio_nand_dev_ready;
|
||||
nand_chip->legacy.dev_ready = tmio_nand_dev_ready;
|
||||
nand_chip->legacy.read_byte = tmio_nand_read_byte;
|
||||
nand_chip->legacy.write_buf = tmio_nand_write_buf;
|
||||
nand_chip->legacy.read_buf = tmio_nand_read_buf;
|
||||
@ -432,7 +432,7 @@ static int tmio_probe(struct platform_device *dev)
|
||||
}
|
||||
|
||||
tmio->irq = irq;
|
||||
nand_chip->waitfunc = tmio_nand_wait;
|
||||
nand_chip->legacy.waitfunc = tmio_nand_wait;
|
||||
|
||||
/* Scan to find existence of the device */
|
||||
retval = nand_scan(nand_chip, 1);
|
||||
|
@ -328,7 +328,7 @@ static int __init txx9ndfmc_probe(struct platform_device *dev)
|
||||
chip->legacy.read_buf = txx9ndfmc_read_buf;
|
||||
chip->legacy.write_buf = txx9ndfmc_write_buf;
|
||||
chip->legacy.cmd_ctrl = txx9ndfmc_cmd_ctrl;
|
||||
chip->dev_ready = txx9ndfmc_dev_ready;
|
||||
chip->legacy.dev_ready = txx9ndfmc_dev_ready;
|
||||
chip->ecc.calculate = txx9ndfmc_calculate_ecc;
|
||||
chip->ecc.correct = txx9ndfmc_correct_data;
|
||||
chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
|
||||
|
@ -175,7 +175,7 @@ static int xway_nand_probe(struct platform_device *pdev)
|
||||
mtd->dev.parent = &pdev->dev;
|
||||
|
||||
data->chip.legacy.cmd_ctrl = xway_cmd_ctrl;
|
||||
data->chip.dev_ready = xway_dev_ready;
|
||||
data->chip.legacy.dev_ready = xway_dev_ready;
|
||||
data->chip.select_chip = xway_select_chip;
|
||||
data->chip.legacy.write_buf = xway_write_buf;
|
||||
data->chip.legacy.read_buf = xway_read_buf;
|
||||
|
@ -919,7 +919,7 @@ static int spinand_probe(struct spi_device *spi_nand)
|
||||
chip->legacy.write_buf = spinand_write_buf;
|
||||
chip->legacy.read_byte = spinand_read_byte;
|
||||
chip->legacy.cmdfunc = spinand_cmdfunc;
|
||||
chip->waitfunc = spinand_wait;
|
||||
chip->legacy.waitfunc = spinand_wait;
|
||||
chip->options |= NAND_CACHEPRG;
|
||||
chip->select_chip = spinand_select_chip;
|
||||
chip->set_features = nand_get_set_features_notsupp;
|
||||
|
@ -1183,6 +1183,10 @@ int nand_op_parser_exec_op(struct nand_chip *chip,
|
||||
* @cmd_ctrl: hardware specific function for controlling ALE/CLE/nCE. Also used
|
||||
* to write command and address
|
||||
* @cmdfunc: hardware specific function for writing commands to the chip.
|
||||
* @dev_ready: hardware specific function for accessing device ready/busy line.
|
||||
* If set to NULL no access to ready/busy is available and the
|
||||
* ready/busy information is read from the chip status register.
|
||||
* @waitfunc: hardware specific function for wait on ready.
|
||||
*
|
||||
* If you look at this structure you're already wrong. These fields/hooks are
|
||||
* all deprecated.
|
||||
@ -1197,6 +1201,8 @@ struct nand_legacy {
|
||||
void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl);
|
||||
void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column,
|
||||
int page_addr);
|
||||
int (*dev_ready)(struct nand_chip *chip);
|
||||
int (*waitfunc)(struct nand_chip *chip);
|
||||
};
|
||||
|
||||
/**
|
||||
@ -1210,16 +1216,10 @@ struct nand_legacy {
|
||||
* @select_chip: [REPLACEABLE] select chip nr
|
||||
* @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
|
||||
* @block_markbad: [REPLACEABLE] mark a block bad
|
||||
* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
|
||||
* device ready/busy line. If set to NULL no access to
|
||||
* ready/busy is available and the ready/busy information
|
||||
* is read from the chip status register.
|
||||
* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
|
||||
* ready.
|
||||
* @exec_op: controller specific method to execute NAND operations.
|
||||
* This method replaces ->cmdfunc(),
|
||||
* ->legacy.{read,write}_{buf,byte,word}(), ->dev_ready()
|
||||
* and ->waifunc().
|
||||
* ->legacy.{read,write}_{buf,byte,word}(),
|
||||
* ->legacy.dev_ready() and ->waifunc().
|
||||
* @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
|
||||
* setting the read-retry mode. Mostly needed for MLC NAND.
|
||||
* @ecc: [BOARDSPECIFIC] ECC control structure
|
||||
@ -1305,8 +1305,6 @@ struct nand_chip {
|
||||
void (*select_chip)(struct nand_chip *chip, int cs);
|
||||
int (*block_bad)(struct nand_chip *chip, loff_t ofs);
|
||||
int (*block_markbad)(struct nand_chip *chip, loff_t ofs);
|
||||
int (*dev_ready)(struct nand_chip *chip);
|
||||
int (*waitfunc)(struct nand_chip *chip);
|
||||
int (*exec_op)(struct nand_chip *chip,
|
||||
const struct nand_operation *op,
|
||||
bool check_only);
|
||||
|
Loading…
Reference in New Issue
Block a user