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[PATCH] PCI: altix: msi support
MSI callouts for altix. Involves a fair amount of code reorg in sn irq.c code as well as adding some extensions to the altix PCI provider abstaction. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Mark Maule
Greg Kroah-Hartman
parent
10083072bf
commit
83821d3f55
@ -58,7 +58,7 @@ static int max_pcibus_number = 255; /* Default highest pci bus number */
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*/
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static dma_addr_t
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sn_default_pci_map(struct pci_dev *pdev, unsigned long paddr, size_t size)
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sn_default_pci_map(struct pci_dev *pdev, unsigned long paddr, size_t size, int type)
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{
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return 0;
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}
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@ -457,13 +457,6 @@ void sn_pci_fixup_slot(struct pci_dev *dev)
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pcidev_info->pdi_sn_irq_info = NULL;
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kfree(sn_irq_info);
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}
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/*
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* MSI currently not supported on altix. Remove this when
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* the MSI abstraction patches are integrated into the kernel
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* (sometime after 2.6.16 releases)
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*/
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dev->no_msi = 1;
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}
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/*
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@ -26,11 +26,11 @@ static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);
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int sn_force_interrupt_flag = 1;
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extern int sn_ioif_inited;
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static struct list_head **sn_irq_lh;
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struct list_head **sn_irq_lh;
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static spinlock_t sn_irq_info_lock = SPIN_LOCK_UNLOCKED; /* non-IRQ lock */
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static inline u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
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u64 sn_irq_info,
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u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
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struct sn_irq_info *sn_irq_info,
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int req_irq, nasid_t req_nasid,
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int req_slice)
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{
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@ -40,12 +40,13 @@ static inline u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
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SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
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(u64) SAL_INTR_ALLOC, (u64) local_nasid,
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(u64) local_widget, (u64) sn_irq_info, (u64) req_irq,
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(u64) local_widget, __pa(sn_irq_info), (u64) req_irq,
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(u64) req_nasid, (u64) req_slice);
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return ret_stuff.status;
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}
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static inline void sn_intr_free(nasid_t local_nasid, int local_widget,
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void sn_intr_free(nasid_t local_nasid, int local_widget,
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struct sn_irq_info *sn_irq_info)
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{
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struct ia64_sal_retval ret_stuff;
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@ -112,73 +113,91 @@ static void sn_end_irq(unsigned int irq)
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static void sn_irq_info_free(struct rcu_head *head);
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struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *sn_irq_info,
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nasid_t nasid, int slice)
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{
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int vector;
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int cpuphys;
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int64_t bridge;
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int local_widget, status;
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nasid_t local_nasid;
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struct sn_irq_info *new_irq_info;
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struct sn_pcibus_provider *pci_provider;
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new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC);
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if (new_irq_info == NULL)
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return NULL;
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memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info));
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bridge = (u64) new_irq_info->irq_bridge;
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if (!bridge) {
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kfree(new_irq_info);
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return NULL; /* irq is not a device interrupt */
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}
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local_nasid = NASID_GET(bridge);
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if (local_nasid & 1)
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local_widget = TIO_SWIN_WIDGETNUM(bridge);
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else
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local_widget = SWIN_WIDGETNUM(bridge);
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vector = sn_irq_info->irq_irq;
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/* Free the old PROM new_irq_info structure */
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sn_intr_free(local_nasid, local_widget, new_irq_info);
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/* Update kernels new_irq_info with new target info */
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unregister_intr_pda(new_irq_info);
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/* allocate a new PROM new_irq_info struct */
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status = sn_intr_alloc(local_nasid, local_widget,
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new_irq_info, vector,
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nasid, slice);
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/* SAL call failed */
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if (status) {
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kfree(new_irq_info);
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return NULL;
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}
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cpuphys = nasid_slice_to_cpuid(nasid, slice);
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new_irq_info->irq_cpuid = cpuphys;
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register_intr_pda(new_irq_info);
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pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];
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/*
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* If this represents a line interrupt, target it. If it's
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* an msi (irq_int_bit < 0), it's already targeted.
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*/
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if (new_irq_info->irq_int_bit >= 0 &&
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pci_provider && pci_provider->target_interrupt)
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(pci_provider->target_interrupt)(new_irq_info);
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spin_lock(&sn_irq_info_lock);
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list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
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spin_unlock(&sn_irq_info_lock);
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call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
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#ifdef CONFIG_SMP
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set_irq_affinity_info((vector & 0xff), cpuphys, 0);
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#endif
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return new_irq_info;
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}
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static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
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{
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struct sn_irq_info *sn_irq_info, *sn_irq_info_safe;
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int cpuid, cpuphys;
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nasid_t nasid;
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int slice;
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cpuid = first_cpu(mask);
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cpuphys = cpu_physical_id(cpuid);
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nasid = cpuid_to_nasid(first_cpu(mask));
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slice = cpuid_to_slice(first_cpu(mask));
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list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
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sn_irq_lh[irq], list) {
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u64 bridge;
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int local_widget, status;
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nasid_t local_nasid;
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struct sn_irq_info *new_irq_info;
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struct sn_pcibus_provider *pci_provider;
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new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC);
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if (new_irq_info == NULL)
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break;
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memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info));
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bridge = (u64) new_irq_info->irq_bridge;
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if (!bridge) {
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kfree(new_irq_info);
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break; /* irq is not a device interrupt */
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}
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local_nasid = NASID_GET(bridge);
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if (local_nasid & 1)
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local_widget = TIO_SWIN_WIDGETNUM(bridge);
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else
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local_widget = SWIN_WIDGETNUM(bridge);
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/* Free the old PROM new_irq_info structure */
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sn_intr_free(local_nasid, local_widget, new_irq_info);
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/* Update kernels new_irq_info with new target info */
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unregister_intr_pda(new_irq_info);
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/* allocate a new PROM new_irq_info struct */
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status = sn_intr_alloc(local_nasid, local_widget,
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__pa(new_irq_info), irq,
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cpuid_to_nasid(cpuid),
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cpuid_to_slice(cpuid));
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/* SAL call failed */
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if (status) {
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kfree(new_irq_info);
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break;
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}
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new_irq_info->irq_cpuid = cpuid;
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register_intr_pda(new_irq_info);
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pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];
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if (pci_provider && pci_provider->target_interrupt)
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(pci_provider->target_interrupt)(new_irq_info);
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spin_lock(&sn_irq_info_lock);
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list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
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spin_unlock(&sn_irq_info_lock);
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call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
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#ifdef CONFIG_SMP
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set_irq_affinity_info((irq & 0xff), cpuphys, 0);
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#endif
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}
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sn_irq_lh[irq], list)
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(void)sn_retarget_vector(sn_irq_info, nasid, slice);
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}
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struct hw_interrupt_type irq_type_sn = {
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@ -11,7 +11,7 @@
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#include <linux/module.h>
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#include <asm/dma.h>
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#include <asm/sn/pcibr_provider.h>
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#include <asm/sn/intr.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/pcidev.h>
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#include <asm/sn/sn_sal.h>
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@ -113,7 +113,8 @@ void *sn_dma_alloc_coherent(struct device *dev, size_t size,
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* resources.
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*/
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*dma_handle = provider->dma_map_consistent(pdev, phys_addr, size);
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*dma_handle = provider->dma_map_consistent(pdev, phys_addr, size,
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SN_DMA_ADDR_PHYS);
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if (!*dma_handle) {
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printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
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free_pages((unsigned long)cpuaddr, get_order(size));
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@ -176,7 +177,7 @@ dma_addr_t sn_dma_map_single(struct device *dev, void *cpu_addr, size_t size,
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BUG_ON(dev->bus != &pci_bus_type);
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phys_addr = __pa(cpu_addr);
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dma_addr = provider->dma_map(pdev, phys_addr, size);
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dma_addr = provider->dma_map(pdev, phys_addr, size, SN_DMA_ADDR_PHYS);
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if (!dma_addr) {
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printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
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return 0;
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@ -260,7 +261,8 @@ int sn_dma_map_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
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for (i = 0; i < nhwentries; i++, sg++) {
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phys_addr = SG_ENT_PHYS_ADDRESS(sg);
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sg->dma_address = provider->dma_map(pdev,
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phys_addr, sg->length);
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phys_addr, sg->length,
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SN_DMA_ADDR_PHYS);
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if (!sg->dma_address) {
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printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
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@ -41,7 +41,7 @@ extern int sn_ioif_inited;
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static dma_addr_t
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pcibr_dmamap_ate32(struct pcidev_info *info,
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u64 paddr, size_t req_size, u64 flags)
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u64 paddr, size_t req_size, u64 flags, int dma_flags)
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{
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struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info;
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@ -81,9 +81,12 @@ pcibr_dmamap_ate32(struct pcidev_info *info,
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if (IS_PCIX(pcibus_info))
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ate_flags &= ~(PCI32_ATE_PREF);
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xio_addr =
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IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) :
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PHYS_TO_TIODMA(paddr);
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if (SN_DMA_ADDRTYPE(dma_flags == SN_DMA_ADDR_PHYS))
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xio_addr = IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) :
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PHYS_TO_TIODMA(paddr);
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else
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xio_addr = paddr;
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offset = IOPGOFF(xio_addr);
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ate = ate_flags | (xio_addr - offset);
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@ -91,6 +94,13 @@ pcibr_dmamap_ate32(struct pcidev_info *info,
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if (IS_PIC_SOFT(pcibus_info)) {
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ate |= (pcibus_info->pbi_hub_xid << PIC_ATE_TARGETID_SHFT);
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}
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/*
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* If we're mapping for MSI, set the MSI bit in the ATE
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*/
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if (dma_flags & SN_DMA_MSI)
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ate |= PCI32_ATE_MSI;
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ate_write(pcibus_info, ate_index, ate_count, ate);
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/*
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@ -105,20 +115,27 @@ pcibr_dmamap_ate32(struct pcidev_info *info,
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if (pcibus_info->pbi_devreg[internal_device] & PCIBR_DEV_SWAP_DIR)
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ATE_SWAP_ON(pci_addr);
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return pci_addr;
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}
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static dma_addr_t
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pcibr_dmatrans_direct64(struct pcidev_info * info, u64 paddr,
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u64 dma_attributes)
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u64 dma_attributes, int dma_flags)
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{
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struct pcibus_info *pcibus_info = (struct pcibus_info *)
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((info->pdi_host_pcidev_info)->pdi_pcibus_info);
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u64 pci_addr;
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/* Translate to Crosstalk View of Physical Address */
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pci_addr = (IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) :
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PHYS_TO_TIODMA(paddr)) | dma_attributes;
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if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS)
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pci_addr = IS_PIC_SOFT(pcibus_info) ?
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PHYS_TO_DMA(paddr) :
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PHYS_TO_TIODMA(paddr) | dma_attributes;
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else
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pci_addr = IS_PIC_SOFT(pcibus_info) ?
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paddr :
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paddr | dma_attributes;
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/* Handle Bus mode */
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if (IS_PCIX(pcibus_info))
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@ -130,7 +147,9 @@ pcibr_dmatrans_direct64(struct pcidev_info * info, u64 paddr,
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((u64) pcibus_info->
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pbi_hub_xid << PIC_PCI64_ATTR_TARG_SHFT);
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} else
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pci_addr |= TIOCP_PCI64_CMDTYPE_MEM;
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pci_addr |= (dma_flags & SN_DMA_MSI) ?
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TIOCP_PCI64_CMDTYPE_MSI :
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TIOCP_PCI64_CMDTYPE_MEM;
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/* If PCI mode, func zero uses VCHAN0, every other func uses VCHAN1 */
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if (!IS_PCIX(pcibus_info) && PCI_FUNC(info->pdi_linux_pcidev->devfn))
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@ -141,7 +160,7 @@ pcibr_dmatrans_direct64(struct pcidev_info * info, u64 paddr,
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static dma_addr_t
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pcibr_dmatrans_direct32(struct pcidev_info * info,
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u64 paddr, size_t req_size, u64 flags)
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u64 paddr, size_t req_size, u64 flags, int dma_flags)
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{
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struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info;
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struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info->
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@ -156,8 +175,14 @@ pcibr_dmatrans_direct32(struct pcidev_info * info,
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return 0;
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}
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xio_addr = IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) :
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PHYS_TO_TIODMA(paddr);
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if (dma_flags & SN_DMA_MSI)
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return 0;
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if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS)
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xio_addr = IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) :
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PHYS_TO_TIODMA(paddr);
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else
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xio_addr = paddr;
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xio_base = pcibus_info->pbi_dir_xbase;
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offset = xio_addr - xio_base;
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@ -327,7 +352,7 @@ void sn_dma_flush(u64 addr)
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*/
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dma_addr_t
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pcibr_dma_map(struct pci_dev * hwdev, unsigned long phys_addr, size_t size)
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pcibr_dma_map(struct pci_dev * hwdev, unsigned long phys_addr, size_t size, int dma_flags)
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{
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dma_addr_t dma_handle;
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struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(hwdev);
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@ -344,11 +369,11 @@ pcibr_dma_map(struct pci_dev * hwdev, unsigned long phys_addr, size_t size)
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*/
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dma_handle = pcibr_dmatrans_direct64(pcidev_info, phys_addr,
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PCI64_ATTR_PREF);
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PCI64_ATTR_PREF, dma_flags);
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} else {
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/* Handle 32-63 bit cards via direct mapping */
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dma_handle = pcibr_dmatrans_direct32(pcidev_info, phys_addr,
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size, 0);
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size, 0, dma_flags);
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if (!dma_handle) {
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/*
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* It is a 32 bit card and we cannot do direct mapping,
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@ -356,7 +381,8 @@ pcibr_dma_map(struct pci_dev * hwdev, unsigned long phys_addr, size_t size)
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*/
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dma_handle = pcibr_dmamap_ate32(pcidev_info, phys_addr,
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size, PCI32_ATE_PREF);
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size, PCI32_ATE_PREF,
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dma_flags);
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}
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}
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@ -365,18 +391,18 @@ pcibr_dma_map(struct pci_dev * hwdev, unsigned long phys_addr, size_t size)
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dma_addr_t
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pcibr_dma_map_consistent(struct pci_dev * hwdev, unsigned long phys_addr,
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size_t size)
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size_t size, int dma_flags)
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{
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dma_addr_t dma_handle;
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struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(hwdev);
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if (hwdev->dev.coherent_dma_mask == ~0UL) {
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dma_handle = pcibr_dmatrans_direct64(pcidev_info, phys_addr,
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PCI64_ATTR_BAR);
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PCI64_ATTR_BAR, dma_flags);
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} else {
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dma_handle = (dma_addr_t) pcibr_dmamap_ate32(pcidev_info,
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phys_addr, size,
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PCI32_ATE_BAR);
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PCI32_ATE_BAR, dma_flags);
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}
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return dma_handle;
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|
||||
@ -515,10 +515,16 @@ tioca_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
|
||||
* use the GART mapped mode.
|
||||
*/
|
||||
static u64
|
||||
tioca_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count)
|
||||
tioca_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count, int dma_flags)
|
||||
{
|
||||
u64 mapaddr;
|
||||
|
||||
/*
|
||||
* Not supported for now ...
|
||||
*/
|
||||
if (dma_flags & SN_DMA_MSI)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* If card is 64 or 48 bit addresable, use a direct mapping. 32
|
||||
* bit direct is so restrictive w.r.t. where the memory resides that
|
||||
|
||||
@ -170,7 +170,8 @@ tioce_mmr_war_post(struct tioce_kernel *kern, void *mmr_addr)
|
||||
(ATE_PAGE((start)+(len)-1, pagesize) - ATE_PAGE(start, pagesize) + 1)
|
||||
|
||||
#define ATE_VALID(ate) ((ate) & (1UL << 63))
|
||||
#define ATE_MAKE(addr, ps) (((addr) & ~ATE_PAGEMASK(ps)) | (1UL << 63))
|
||||
#define ATE_MAKE(addr, ps, msi) \
|
||||
(((addr) & ~ATE_PAGEMASK(ps)) | (1UL << 63) | ((msi)?(1UL << 62):0))
|
||||
|
||||
/*
|
||||
* Flavors of ate-based mapping supported by tioce_alloc_map()
|
||||
@ -196,15 +197,17 @@ tioce_mmr_war_post(struct tioce_kernel *kern, void *mmr_addr)
|
||||
*
|
||||
* 63 - must be 1 to indicate d64 mode to CE hardware
|
||||
* 62 - barrier bit ... controlled with tioce_dma_barrier()
|
||||
* 61 - 0 since this is not an MSI transaction
|
||||
* 61 - msi bit ... specified through dma_flags
|
||||
* 60:54 - reserved, MBZ
|
||||
*/
|
||||
static u64
|
||||
tioce_dma_d64(unsigned long ct_addr)
|
||||
tioce_dma_d64(unsigned long ct_addr, int dma_flags)
|
||||
{
|
||||
u64 bus_addr;
|
||||
|
||||
bus_addr = ct_addr | (1UL << 63);
|
||||
if (dma_flags & SN_DMA_MSI)
|
||||
bus_addr |= (1UL << 61);
|
||||
|
||||
return bus_addr;
|
||||
}
|
||||
@ -261,7 +264,7 @@ pcidev_to_tioce(struct pci_dev *pdev, struct tioce **base,
|
||||
*/
|
||||
static u64
|
||||
tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
|
||||
u64 ct_addr, int len)
|
||||
u64 ct_addr, int len, int dma_flags)
|
||||
{
|
||||
int i;
|
||||
int j;
|
||||
@ -270,6 +273,7 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
|
||||
int entries;
|
||||
int nates;
|
||||
u64 pagesize;
|
||||
int msi_capable, msi_wanted;
|
||||
u64 *ate_shadow;
|
||||
u64 *ate_reg;
|
||||
u64 addr;
|
||||
@ -291,6 +295,7 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
|
||||
ate_reg = ce_mmr->ce_ure_ate3240;
|
||||
pagesize = ce_kern->ce_ate3240_pagesize;
|
||||
bus_base = TIOCE_M32_MIN;
|
||||
msi_capable = 1;
|
||||
break;
|
||||
case TIOCE_ATE_M40:
|
||||
first = 0;
|
||||
@ -299,6 +304,7 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
|
||||
ate_reg = ce_mmr->ce_ure_ate40;
|
||||
pagesize = MB(64);
|
||||
bus_base = TIOCE_M40_MIN;
|
||||
msi_capable = 0;
|
||||
break;
|
||||
case TIOCE_ATE_M40S:
|
||||
/*
|
||||
@ -311,11 +317,16 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
|
||||
ate_reg = ce_mmr->ce_ure_ate3240;
|
||||
pagesize = GB(16);
|
||||
bus_base = TIOCE_M40S_MIN;
|
||||
msi_capable = 0;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
msi_wanted = dma_flags & SN_DMA_MSI;
|
||||
if (msi_wanted && !msi_capable)
|
||||
return 0;
|
||||
|
||||
nates = ATE_NPAGES(ct_addr, len, pagesize);
|
||||
if (nates > entries)
|
||||
return 0;
|
||||
@ -344,7 +355,7 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
|
||||
for (j = 0; j < nates; j++) {
|
||||
u64 ate;
|
||||
|
||||
ate = ATE_MAKE(addr, pagesize);
|
||||
ate = ATE_MAKE(addr, pagesize, msi_wanted);
|
||||
ate_shadow[i + j] = ate;
|
||||
tioce_mmr_storei(ce_kern, &ate_reg[i + j], ate);
|
||||
addr += pagesize;
|
||||
@ -371,7 +382,7 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
|
||||
* Map @paddr into 32-bit bus space of the CE associated with @pcidev_info.
|
||||
*/
|
||||
static u64
|
||||
tioce_dma_d32(struct pci_dev *pdev, u64 ct_addr)
|
||||
tioce_dma_d32(struct pci_dev *pdev, u64 ct_addr, int dma_flags)
|
||||
{
|
||||
int dma_ok;
|
||||
int port;
|
||||
@ -381,6 +392,9 @@ tioce_dma_d32(struct pci_dev *pdev, u64 ct_addr)
|
||||
u64 ct_lower;
|
||||
dma_addr_t bus_addr;
|
||||
|
||||
if (dma_flags & SN_DMA_MSI)
|
||||
return 0;
|
||||
|
||||
ct_upper = ct_addr & ~0x3fffffffUL;
|
||||
ct_lower = ct_addr & 0x3fffffffUL;
|
||||
|
||||
@ -507,7 +521,7 @@ tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
|
||||
*/
|
||||
static u64
|
||||
tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count,
|
||||
int barrier)
|
||||
int barrier, int dma_flags)
|
||||
{
|
||||
unsigned long flags;
|
||||
u64 ct_addr;
|
||||
@ -523,15 +537,18 @@ tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count,
|
||||
if (dma_mask < 0x7fffffffUL)
|
||||
return 0;
|
||||
|
||||
ct_addr = PHYS_TO_TIODMA(paddr);
|
||||
if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS)
|
||||
ct_addr = PHYS_TO_TIODMA(paddr);
|
||||
else
|
||||
ct_addr = paddr;
|
||||
|
||||
/*
|
||||
* If the device can generate 64 bit addresses, create a D64 map.
|
||||
* Since this should never fail, bypass the rest of the checks.
|
||||
*/
|
||||
if (dma_mask == ~0UL) {
|
||||
mapaddr = tioce_dma_d64(ct_addr);
|
||||
goto dma_map_done;
|
||||
mapaddr = tioce_dma_d64(ct_addr, dma_flags);
|
||||
if (mapaddr)
|
||||
goto dma_map_done;
|
||||
}
|
||||
|
||||
pcidev_to_tioce(pdev, NULL, &ce_kern, &port);
|
||||
@ -574,18 +591,22 @@ tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count,
|
||||
|
||||
if (byte_count > MB(64)) {
|
||||
mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40S,
|
||||
port, ct_addr, byte_count);
|
||||
port, ct_addr, byte_count,
|
||||
dma_flags);
|
||||
if (!mapaddr)
|
||||
mapaddr =
|
||||
tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1,
|
||||
ct_addr, byte_count);
|
||||
ct_addr, byte_count,
|
||||
dma_flags);
|
||||
} else {
|
||||
mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1,
|
||||
ct_addr, byte_count);
|
||||
ct_addr, byte_count,
|
||||
dma_flags);
|
||||
if (!mapaddr)
|
||||
mapaddr =
|
||||
tioce_alloc_map(ce_kern, TIOCE_ATE_M40S,
|
||||
port, ct_addr, byte_count);
|
||||
port, ct_addr, byte_count,
|
||||
dma_flags);
|
||||
}
|
||||
}
|
||||
|
||||
@ -593,7 +614,7 @@ tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count,
|
||||
* 32-bit direct is the next mode to try
|
||||
*/
|
||||
if (!mapaddr && dma_mask >= 0xffffffffUL)
|
||||
mapaddr = tioce_dma_d32(pdev, ct_addr);
|
||||
mapaddr = tioce_dma_d32(pdev, ct_addr, dma_flags);
|
||||
|
||||
/*
|
||||
* Last resort, try 32-bit ATE-based map.
|
||||
@ -601,7 +622,7 @@ tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count,
|
||||
if (!mapaddr)
|
||||
mapaddr =
|
||||
tioce_alloc_map(ce_kern, TIOCE_ATE_M32, -1, ct_addr,
|
||||
byte_count);
|
||||
byte_count, dma_flags);
|
||||
|
||||
spin_unlock_irqrestore(&ce_kern->ce_lock, flags);
|
||||
|
||||
@ -622,9 +643,9 @@ dma_map_done:
|
||||
* in the address.
|
||||
*/
|
||||
static u64
|
||||
tioce_dma(struct pci_dev *pdev, u64 paddr, size_t byte_count)
|
||||
tioce_dma(struct pci_dev *pdev, u64 paddr, size_t byte_count, int dma_flags)
|
||||
{
|
||||
return tioce_do_dma_map(pdev, paddr, byte_count, 0);
|
||||
return tioce_do_dma_map(pdev, paddr, byte_count, 0, dma_flags);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -636,9 +657,9 @@ tioce_dma(struct pci_dev *pdev, u64 paddr, size_t byte_count)
|
||||
* Simply call tioce_do_dma_map() to create a map with the barrier bit set
|
||||
* in the address.
|
||||
*/ static u64
|
||||
tioce_dma_consistent(struct pci_dev *pdev, u64 paddr, size_t byte_count)
|
||||
tioce_dma_consistent(struct pci_dev *pdev, u64 paddr, size_t byte_count, int dma_flags)
|
||||
{
|
||||
return tioce_do_dma_map(pdev, paddr, byte_count, 1);
|
||||
return tioce_do_dma_map(pdev, paddr, byte_count, 1, dma_flags);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -696,7 +717,7 @@ tioce_reserve_m32(struct tioce_kernel *ce_kern, u64 base, u64 limit)
|
||||
while (ate_index <= last_ate) {
|
||||
u64 ate;
|
||||
|
||||
ate = ATE_MAKE(0xdeadbeef, ps);
|
||||
ate = ATE_MAKE(0xdeadbeef, ps, 0);
|
||||
ce_kern->ce_ate3240_shadow[ate_index] = ate;
|
||||
tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_ate3240[ate_index],
|
||||
ate);
|
||||
|
||||
@ -6,13 +6,205 @@
|
||||
* Copyright (C) 2006 Silicon Graphics, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
#include <asm/errno.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/cpumask.h>
|
||||
|
||||
#include <asm/sn/addrs.h>
|
||||
#include <asm/sn/intr.h>
|
||||
#include <asm/sn/pcibus_provider_defs.h>
|
||||
#include <asm/sn/pcidev.h>
|
||||
#include <asm/sn/nodepda.h>
|
||||
|
||||
#include "msi.h"
|
||||
|
||||
struct sn_msi_info {
|
||||
u64 pci_addr;
|
||||
struct sn_irq_info *sn_irq_info;
|
||||
};
|
||||
|
||||
static struct sn_msi_info *sn_msi_info;
|
||||
|
||||
static void
|
||||
sn_msi_teardown(unsigned int vector)
|
||||
{
|
||||
nasid_t nasid;
|
||||
int widget;
|
||||
struct pci_dev *pdev;
|
||||
struct pcidev_info *sn_pdev;
|
||||
struct sn_irq_info *sn_irq_info;
|
||||
struct pcibus_bussoft *bussoft;
|
||||
struct sn_pcibus_provider *provider;
|
||||
|
||||
sn_irq_info = sn_msi_info[vector].sn_irq_info;
|
||||
if (sn_irq_info == NULL || sn_irq_info->irq_int_bit >= 0)
|
||||
return;
|
||||
|
||||
sn_pdev = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
|
||||
pdev = sn_pdev->pdi_linux_pcidev;
|
||||
provider = SN_PCIDEV_BUSPROVIDER(pdev);
|
||||
|
||||
(*provider->dma_unmap)(pdev,
|
||||
sn_msi_info[vector].pci_addr,
|
||||
PCI_DMA_FROMDEVICE);
|
||||
sn_msi_info[vector].pci_addr = 0;
|
||||
|
||||
bussoft = SN_PCIDEV_BUSSOFT(pdev);
|
||||
nasid = NASID_GET(bussoft->bs_base);
|
||||
widget = (nasid & 1) ?
|
||||
TIO_SWIN_WIDGETNUM(bussoft->bs_base) :
|
||||
SWIN_WIDGETNUM(bussoft->bs_base);
|
||||
|
||||
sn_intr_free(nasid, widget, sn_irq_info);
|
||||
sn_msi_info[vector].sn_irq_info = NULL;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
int
|
||||
sn_msi_setup(struct pci_dev *pdev, unsigned int vector,
|
||||
u32 *addr_hi, u32 *addr_lo, u32 *data)
|
||||
{
|
||||
int widget;
|
||||
int status;
|
||||
nasid_t nasid;
|
||||
u64 bus_addr;
|
||||
struct sn_irq_info *sn_irq_info;
|
||||
struct pcibus_bussoft *bussoft = SN_PCIDEV_BUSSOFT(pdev);
|
||||
struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
|
||||
|
||||
if (bussoft == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
if (provider == NULL || provider->dma_map_consistent == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* Set up the vector plumbing. Let the prom (via sn_intr_alloc)
|
||||
* decide which cpu to direct this msi at by default.
|
||||
*/
|
||||
|
||||
nasid = NASID_GET(bussoft->bs_base);
|
||||
widget = (nasid & 1) ?
|
||||
TIO_SWIN_WIDGETNUM(bussoft->bs_base) :
|
||||
SWIN_WIDGETNUM(bussoft->bs_base);
|
||||
|
||||
sn_irq_info = kzalloc(sizeof(struct sn_irq_info), GFP_KERNEL);
|
||||
if (! sn_irq_info)
|
||||
return -ENOMEM;
|
||||
|
||||
status = sn_intr_alloc(nasid, widget, sn_irq_info, vector, -1, -1);
|
||||
if (status) {
|
||||
kfree(sn_irq_info);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
sn_irq_info->irq_int_bit = -1; /* mark this as an MSI irq */
|
||||
sn_irq_fixup(pdev, sn_irq_info);
|
||||
|
||||
/* Prom probably should fill these in, but doesn't ... */
|
||||
sn_irq_info->irq_bridge_type = bussoft->bs_asic_type;
|
||||
sn_irq_info->irq_bridge = (void *)bussoft->bs_base;
|
||||
|
||||
/*
|
||||
* Map the xio address into bus space
|
||||
*/
|
||||
bus_addr = (*provider->dma_map_consistent)(pdev,
|
||||
sn_irq_info->irq_xtalkaddr,
|
||||
sizeof(sn_irq_info->irq_xtalkaddr),
|
||||
SN_DMA_MSI|SN_DMA_ADDR_XIO);
|
||||
if (! bus_addr) {
|
||||
sn_intr_free(nasid, widget, sn_irq_info);
|
||||
kfree(sn_irq_info);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
sn_msi_info[vector].sn_irq_info = sn_irq_info;
|
||||
sn_msi_info[vector].pci_addr = bus_addr;
|
||||
|
||||
*addr_hi = (u32)(bus_addr >> 32);
|
||||
*addr_lo = (u32)(bus_addr & 0x00000000ffffffff);
|
||||
|
||||
/*
|
||||
* In the SN platform, bit 16 is a "send vector" bit which
|
||||
* must be present in order to move the vector through the system.
|
||||
*/
|
||||
*data = 0x100 + (unsigned int)vector;
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
set_irq_affinity_info((vector & 0xff), sn_irq_info->irq_cpuid, 0);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
sn_msi_target(unsigned int vector, unsigned int cpu,
|
||||
u32 *addr_hi, u32 *addr_lo)
|
||||
{
|
||||
int slice;
|
||||
nasid_t nasid;
|
||||
u64 bus_addr;
|
||||
struct pci_dev *pdev;
|
||||
struct pcidev_info *sn_pdev;
|
||||
struct sn_irq_info *sn_irq_info;
|
||||
struct sn_irq_info *new_irq_info;
|
||||
struct sn_pcibus_provider *provider;
|
||||
|
||||
sn_irq_info = sn_msi_info[vector].sn_irq_info;
|
||||
if (sn_irq_info == NULL || sn_irq_info->irq_int_bit >= 0)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Release XIO resources for the old MSI PCI address
|
||||
*/
|
||||
|
||||
sn_pdev = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
|
||||
pdev = sn_pdev->pdi_linux_pcidev;
|
||||
provider = SN_PCIDEV_BUSPROVIDER(pdev);
|
||||
|
||||
bus_addr = (u64)(*addr_hi) << 32 | (u64)(*addr_lo);
|
||||
(*provider->dma_unmap)(pdev, bus_addr, PCI_DMA_FROMDEVICE);
|
||||
sn_msi_info[vector].pci_addr = 0;
|
||||
|
||||
nasid = cpuid_to_nasid(cpu);
|
||||
slice = cpuid_to_slice(cpu);
|
||||
|
||||
new_irq_info = sn_retarget_vector(sn_irq_info, nasid, slice);
|
||||
sn_msi_info[vector].sn_irq_info = new_irq_info;
|
||||
if (new_irq_info == NULL)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Map the xio address into bus space
|
||||
*/
|
||||
|
||||
bus_addr = (*provider->dma_map_consistent)(pdev,
|
||||
new_irq_info->irq_xtalkaddr,
|
||||
sizeof(new_irq_info->irq_xtalkaddr),
|
||||
SN_DMA_MSI|SN_DMA_ADDR_XIO);
|
||||
|
||||
sn_msi_info[vector].pci_addr = bus_addr;
|
||||
*addr_hi = (u32)(bus_addr >> 32);
|
||||
*addr_lo = (u32)(bus_addr & 0x00000000ffffffff);
|
||||
}
|
||||
|
||||
struct msi_ops sn_msi_ops = {
|
||||
.setup = sn_msi_setup,
|
||||
.teardown = sn_msi_teardown,
|
||||
#ifdef CONFIG_SMP
|
||||
.target = sn_msi_target,
|
||||
#endif
|
||||
};
|
||||
|
||||
int
|
||||
sn_msi_init(void)
|
||||
{
|
||||
/*
|
||||
* return error until MSI is supported on altix platforms
|
||||
*/
|
||||
return -EINVAL;
|
||||
sn_msi_info =
|
||||
kzalloc(sizeof(struct sn_msi_info) * NR_VECTORS, GFP_KERNEL);
|
||||
if (! sn_msi_info)
|
||||
return -ENOMEM;
|
||||
|
||||
msi_register(&sn_msi_ops);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -10,6 +10,7 @@
|
||||
#define _ASM_IA64_SN_INTR_H
|
||||
|
||||
#include <linux/rcupdate.h>
|
||||
#include <asm/sn/types.h>
|
||||
|
||||
#define SGI_UART_VECTOR 0xe9
|
||||
|
||||
@ -40,6 +41,7 @@ struct sn_irq_info {
|
||||
int irq_cpuid; /* kernel logical cpuid */
|
||||
int irq_irq; /* the IRQ number */
|
||||
int irq_int_bit; /* Bridge interrupt pin */
|
||||
/* <0 means MSI */
|
||||
u64 irq_xtalkaddr; /* xtalkaddr IRQ is sent to */
|
||||
int irq_bridge_type;/* pciio asic type (pciio.h) */
|
||||
void *irq_bridge; /* bridge generating irq */
|
||||
@ -53,6 +55,12 @@ struct sn_irq_info {
|
||||
};
|
||||
|
||||
extern void sn_send_IPI_phys(int, long, int, int);
|
||||
extern u64 sn_intr_alloc(nasid_t, int,
|
||||
struct sn_irq_info *,
|
||||
int, nasid_t, int);
|
||||
extern void sn_intr_free(nasid_t, int, struct sn_irq_info *);
|
||||
extern struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *, nasid_t, int);
|
||||
extern struct list_head **sn_irq_lh;
|
||||
|
||||
#define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector)
|
||||
|
||||
|
||||
@ -55,6 +55,7 @@
|
||||
#define PCI32_ATE_V (0x1 << 0)
|
||||
#define PCI32_ATE_CO (0x1 << 1)
|
||||
#define PCI32_ATE_PREC (0x1 << 2)
|
||||
#define PCI32_ATE_MSI (0x1 << 2)
|
||||
#define PCI32_ATE_PREF (0x1 << 3)
|
||||
#define PCI32_ATE_BAR (0x1 << 4)
|
||||
#define PCI32_ATE_ADDR_SHFT 12
|
||||
@ -117,8 +118,8 @@ struct pcibus_info {
|
||||
|
||||
extern int pcibr_init_provider(void);
|
||||
extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *);
|
||||
extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t);
|
||||
extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t);
|
||||
extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t, int type);
|
||||
extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t, int type);
|
||||
extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
|
||||
|
||||
/*
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
|
||||
* Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
|
||||
#define _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
|
||||
@ -45,13 +45,24 @@ struct pci_controller;
|
||||
*/
|
||||
|
||||
struct sn_pcibus_provider {
|
||||
dma_addr_t (*dma_map)(struct pci_dev *, unsigned long, size_t);
|
||||
dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t);
|
||||
dma_addr_t (*dma_map)(struct pci_dev *, unsigned long, size_t, int flags);
|
||||
dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t, int flags);
|
||||
void (*dma_unmap)(struct pci_dev *, dma_addr_t, int);
|
||||
void * (*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *);
|
||||
void (*force_interrupt)(struct sn_irq_info *);
|
||||
void (*target_interrupt)(struct sn_irq_info *);
|
||||
};
|
||||
|
||||
/*
|
||||
* Flags used by the map interfaces
|
||||
* bits 3:0 specifies format of passed in address
|
||||
* bit 4 specifies that address is to be used for MSI
|
||||
*/
|
||||
|
||||
#define SN_DMA_ADDRTYPE(x) ((x) & 0xf)
|
||||
#define SN_DMA_ADDR_PHYS 1 /* address is an xio address. */
|
||||
#define SN_DMA_ADDR_XIO 2 /* address is phys memory */
|
||||
#define SN_DMA_MSI 0x10 /* Bus address is to be used for MSI */
|
||||
|
||||
extern struct sn_pcibus_provider *sn_pci_provider[];
|
||||
#endif /* _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H */
|
||||
|
||||
@ -3,13 +3,14 @@
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2003-2004 Silicon Graphics, Inc. All rights reserved.
|
||||
* Copyright (C) 2003-2005 Silicon Graphics, Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef _ASM_IA64_SN_PCI_TIOCP_H
|
||||
#define _ASM_IA64_SN_PCI_TIOCP_H
|
||||
|
||||
#define TIOCP_HOST_INTR_ADDR 0x003FFFFFFFFFFFFFUL
|
||||
#define TIOCP_PCI64_CMDTYPE_MEM (0x1ull << 60)
|
||||
#define TIOCP_PCI64_CMDTYPE_MSI (0x3ull << 60)
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
|
||||
Loading…
Reference in New Issue
Block a user