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powerpc/virtex: Use generic xilinx irqchip driver
The Xilinx interrupt controller driver is now available in drivers/irqchip. Switch to using that driver. Acked-by: Michael Ellerman <mpe@ellerman.id.au> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Zubair Lutfullah Kakakhel
Marc Zyngier
parent
8a11da598e
commit
8328255ff8
@ -14,7 +14,7 @@
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#ifdef __KERNEL__
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extern void __init xilinx_intc_init_tree(void);
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extern unsigned int xilinx_intc_get_irq(void);
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extern unsigned int xintc_get_irq(void);
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_XILINX_INTC_H */
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@ -64,6 +64,7 @@ config XILINX_VIRTEX_GENERIC_BOARD
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default n
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select XILINX_VIRTEX_II_PRO
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select XILINX_VIRTEX_4_FX
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select XILINX_INTC
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help
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This option enables generic support for Xilinx Virtex based boards.
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@ -48,7 +48,7 @@ define_machine(virtex) {
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.probe = virtex_probe,
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.setup_arch = xilinx_pci_init,
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.init_IRQ = xilinx_intc_init_tree,
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.get_irq = xilinx_intc_get_irq,
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.get_irq = xintc_get_irq,
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.restart = ppc4xx_reset_system,
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.calibrate_decr = generic_calibrate_decr,
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};
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@ -241,6 +241,7 @@ config XILINX_VIRTEX440_GENERIC_BOARD
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depends on 44x
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default n
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select XILINX_VIRTEX_5_FXT
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select XILINX_INTC
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help
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This option enables generic support for Xilinx Virtex based boards
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that use a 440 based processor in the Virtex 5 FXT FPGA architecture.
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@ -54,7 +54,7 @@ define_machine(virtex) {
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.probe = virtex_probe,
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.setup_arch = xilinx_pci_init,
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.init_IRQ = xilinx_intc_init_tree,
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.get_irq = xilinx_intc_get_irq,
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.get_irq = xintc_get_irq,
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.calibrate_decr = generic_calibrate_decr,
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.restart = ppc4xx_reset_system,
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};
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@ -29,194 +29,7 @@
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#include <asm/processor.h>
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#include <asm/i8259.h>
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#include <asm/irq.h>
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/*
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* INTC Registers
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*/
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#define XINTC_ISR 0 /* Interrupt Status */
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#define XINTC_IPR 4 /* Interrupt Pending */
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#define XINTC_IER 8 /* Interrupt Enable */
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#define XINTC_IAR 12 /* Interrupt Acknowledge */
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#define XINTC_SIE 16 /* Set Interrupt Enable bits */
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#define XINTC_CIE 20 /* Clear Interrupt Enable bits */
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#define XINTC_IVR 24 /* Interrupt Vector */
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#define XINTC_MER 28 /* Master Enable */
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static struct irq_domain *master_irqhost;
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#define XILINX_INTC_MAXIRQS (32)
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/* The following table allows the interrupt type, edge or level,
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* to be cached after being read from the device tree until the interrupt
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* is mapped
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*/
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static int xilinx_intc_typetable[XILINX_INTC_MAXIRQS];
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/* Map the interrupt type from the device tree to the interrupt types
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* used by the interrupt subsystem
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*/
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static unsigned char xilinx_intc_map_senses[] = {
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IRQ_TYPE_EDGE_RISING,
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IRQ_TYPE_EDGE_FALLING,
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IRQ_TYPE_LEVEL_HIGH,
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IRQ_TYPE_LEVEL_LOW,
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};
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/*
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* The interrupt controller is setup such that it doesn't work well with
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* the level interrupt handler in the kernel because the handler acks the
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* interrupt before calling the application interrupt handler. To deal with
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* that, we use 2 different irq chips so that different functions can be
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* used for level and edge type interrupts.
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*
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* IRQ Chip common (across level and edge) operations
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*/
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static void xilinx_intc_mask(struct irq_data *d)
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{
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int irq = irqd_to_hwirq(d);
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void * regs = irq_data_get_irq_chip_data(d);
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pr_debug("mask: %d\n", irq);
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out_be32(regs + XINTC_CIE, 1 << irq);
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}
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static int xilinx_intc_set_type(struct irq_data *d, unsigned int flow_type)
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{
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return 0;
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}
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/*
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* IRQ Chip level operations
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*/
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static void xilinx_intc_level_unmask(struct irq_data *d)
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{
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int irq = irqd_to_hwirq(d);
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void * regs = irq_data_get_irq_chip_data(d);
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pr_debug("unmask: %d\n", irq);
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out_be32(regs + XINTC_SIE, 1 << irq);
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/* ack level irqs because they can't be acked during
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* ack function since the handle_level_irq function
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* acks the irq before calling the inerrupt handler
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*/
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out_be32(regs + XINTC_IAR, 1 << irq);
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}
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static struct irq_chip xilinx_intc_level_irqchip = {
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.name = "Xilinx Level INTC",
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.irq_mask = xilinx_intc_mask,
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.irq_mask_ack = xilinx_intc_mask,
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.irq_unmask = xilinx_intc_level_unmask,
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.irq_set_type = xilinx_intc_set_type,
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};
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/*
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* IRQ Chip edge operations
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*/
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static void xilinx_intc_edge_unmask(struct irq_data *d)
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{
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int irq = irqd_to_hwirq(d);
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void *regs = irq_data_get_irq_chip_data(d);
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pr_debug("unmask: %d\n", irq);
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out_be32(regs + XINTC_SIE, 1 << irq);
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}
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static void xilinx_intc_edge_ack(struct irq_data *d)
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{
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int irq = irqd_to_hwirq(d);
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void * regs = irq_data_get_irq_chip_data(d);
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pr_debug("ack: %d\n", irq);
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out_be32(regs + XINTC_IAR, 1 << irq);
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}
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static struct irq_chip xilinx_intc_edge_irqchip = {
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.name = "Xilinx Edge INTC",
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.irq_mask = xilinx_intc_mask,
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.irq_unmask = xilinx_intc_edge_unmask,
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.irq_ack = xilinx_intc_edge_ack,
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.irq_set_type = xilinx_intc_set_type,
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};
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/*
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* IRQ Host operations
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*/
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/**
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* xilinx_intc_xlate - translate virq# from device tree interrupts property
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*/
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static int xilinx_intc_xlate(struct irq_domain *h, struct device_node *ct,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_flags)
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{
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if ((intsize < 2) || (intspec[0] >= XILINX_INTC_MAXIRQS))
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return -EINVAL;
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/* keep a copy of the interrupt type til the interrupt is mapped
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*/
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xilinx_intc_typetable[intspec[0]] = xilinx_intc_map_senses[intspec[1]];
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/* Xilinx uses 2 interrupt entries, the 1st being the h/w
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* interrupt number, the 2nd being the interrupt type, edge or level
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*/
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*out_hwirq = intspec[0];
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*out_flags = xilinx_intc_map_senses[intspec[1]];
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return 0;
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}
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static int xilinx_intc_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t irq)
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{
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irq_set_chip_data(virq, h->host_data);
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if (xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_HIGH ||
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xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_LOW) {
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irq_set_chip_and_handler(virq, &xilinx_intc_level_irqchip,
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handle_level_irq);
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} else {
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irq_set_chip_and_handler(virq, &xilinx_intc_edge_irqchip,
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handle_edge_irq);
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}
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return 0;
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}
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static const struct irq_domain_ops xilinx_intc_ops = {
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.map = xilinx_intc_map,
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.xlate = xilinx_intc_xlate,
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};
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struct irq_domain * __init
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xilinx_intc_init(struct device_node *np)
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{
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struct irq_domain * irq;
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void * regs;
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/* Find and map the intc registers */
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regs = of_iomap(np, 0);
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if (!regs) {
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pr_err("xilinx_intc: could not map registers\n");
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return NULL;
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}
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/* Setup interrupt controller */
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out_be32(regs + XINTC_IER, 0); /* disable all irqs */
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out_be32(regs + XINTC_IAR, ~(u32) 0); /* Acknowledge pending irqs */
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out_be32(regs + XINTC_MER, 0x3UL); /* Turn on the Master Enable. */
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/* Allocate and initialize an irq_domain structure. */
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irq = irq_domain_add_linear(np, XILINX_INTC_MAXIRQS, &xilinx_intc_ops,
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regs);
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if (!irq)
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panic(__FILE__ ": Cannot allocate IRQ host\n");
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return irq;
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}
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int xilinx_intc_get_irq(void)
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{
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void * regs = master_irqhost->host_data;
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pr_debug("get_irq:\n");
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return irq_linear_revmap(master_irqhost, in_be32(regs + XINTC_IVR));
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}
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#include <linux/irqchip.h>
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#if defined(CONFIG_PPC_I8259)
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/*
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@ -265,31 +78,11 @@ static void __init xilinx_i8259_setup_cascade(void)
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static inline void xilinx_i8259_setup_cascade(void) { return; }
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#endif /* defined(CONFIG_PPC_I8259) */
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static const struct of_device_id xilinx_intc_match[] __initconst = {
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{ .compatible = "xlnx,opb-intc-1.00.c", },
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{ .compatible = "xlnx,xps-intc-1.00.a", },
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{}
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};
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/*
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* Initialize master Xilinx interrupt controller
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*/
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void __init xilinx_intc_init_tree(void)
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{
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struct device_node *np;
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/* find top level interrupt controller */
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for_each_matching_node(np, xilinx_intc_match) {
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if (!of_get_property(np, "interrupts", NULL))
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break;
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}
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BUG_ON(!np);
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master_irqhost = xilinx_intc_init(np);
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BUG_ON(!master_irqhost);
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irq_set_default_host(master_irqhost);
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of_node_put(np);
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irqchip_init();
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xilinx_i8259_setup_cascade();
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}
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@ -237,4 +237,5 @@ err_alloc:
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}
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IRQCHIP_DECLARE(xilinx_intc, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
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IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
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IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init);
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