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PCI: hv: Make the code arch neutral by adding arch specific interfaces
Encapsulate arch dependencies in Hyper-V vPCI through a set of arch-dependent interfaces. Adding these arch specific interfaces will allow for an implementation for other architectures, such as arm64. There are no functional changes expected from this patch. Link: https://lore.kernel.org/r/1641411156-31705-2-git-send-email-sunilmut@linux.microsoft.com Signed-off-by: Sunil Muthuswamy <sunilmut@microsoft.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Boqun Feng <boqun.feng@gmail.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Michael Kelley <mikelley@microsoft.com>
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@ -602,6 +602,39 @@ enum hv_interrupt_type {
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HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A,
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};
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union hv_msi_address_register {
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u32 as_uint32;
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struct {
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u32 reserved1:2;
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u32 destination_mode:1;
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u32 redirection_hint:1;
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u32 reserved2:8;
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u32 destination_id:8;
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u32 msi_base:12;
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};
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} __packed;
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union hv_msi_data_register {
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u32 as_uint32;
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struct {
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u32 vector:8;
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u32 delivery_mode:3;
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u32 reserved1:3;
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u32 level_assert:1;
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u32 trigger_mode:1;
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u32 reserved2:16;
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};
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} __packed;
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/* HvRetargetDeviceInterrupt hypercall */
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union hv_msi_entry {
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u64 as_uint64;
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struct {
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union hv_msi_address_register address;
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union hv_msi_data_register data;
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} __packed;
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};
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#include <asm-generic/hyperv-tlfs.h>
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#endif
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@ -169,13 +169,6 @@ bool hv_vcpu_is_preempted(int vcpu);
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static inline void hv_apic_init(void) {}
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#endif
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static inline void hv_set_msi_entry_from_desc(union hv_msi_entry *msi_entry,
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struct msi_desc *msi_desc)
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{
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msi_entry->address.as_uint32 = msi_desc->msg.address_lo;
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msi_entry->data.as_uint32 = msi_desc->msg.data;
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}
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struct irq_domain *hv_create_pci_msi_domain(void);
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int hv_map_ioapic_interrupt(int ioapic_id, bool level, int vcpu, int vector,
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@ -43,9 +43,6 @@
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#include <linux/pci-ecam.h>
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#include <linux/delay.h>
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#include <linux/semaphore.h>
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#include <linux/irqdomain.h>
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#include <asm/irqdomain.h>
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#include <asm/apic.h>
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include <linux/hyperv.h>
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@ -583,6 +580,42 @@ struct hv_pci_compl {
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static void hv_pci_onchannelcallback(void *context);
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#ifdef CONFIG_X86
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#define DELIVERY_MODE APIC_DELIVERY_MODE_FIXED
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#define FLOW_HANDLER handle_edge_irq
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#define FLOW_NAME "edge"
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static int hv_pci_irqchip_init(void)
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{
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return 0;
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}
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static struct irq_domain *hv_pci_get_root_domain(void)
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{
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return x86_vector_domain;
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}
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static unsigned int hv_msi_get_int_vector(struct irq_data *data)
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{
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struct irq_cfg *cfg = irqd_cfg(data);
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return cfg->vector;
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}
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static void hv_set_msi_entry_from_desc(union hv_msi_entry *msi_entry,
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struct msi_desc *msi_desc)
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{
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msi_entry->address.as_uint32 = msi_desc->msg.address_lo;
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msi_entry->data.as_uint32 = msi_desc->msg.data;
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}
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static int hv_msi_prepare(struct irq_domain *domain, struct device *dev,
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int nvec, msi_alloc_info_t *info)
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{
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return pci_msi_prepare(domain, dev, nvec, info);
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}
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#endif /* CONFIG_X86 */
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/**
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* hv_pci_generic_compl() - Invoked for a completion packet
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* @context: Set up by the sender of the packet.
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@ -1191,14 +1224,6 @@ static void hv_msi_free(struct irq_domain *domain, struct msi_domain_info *info,
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put_pcichild(hpdev);
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}
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static int hv_set_affinity(struct irq_data *data, const struct cpumask *dest,
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bool force)
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{
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struct irq_data *parent = data->parent_data;
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return parent->chip->irq_set_affinity(parent, dest, force);
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}
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static void hv_irq_mask(struct irq_data *data)
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{
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pci_msi_mask_irq(data);
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@ -1217,7 +1242,6 @@ static void hv_irq_mask(struct irq_data *data)
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static void hv_irq_unmask(struct irq_data *data)
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{
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struct msi_desc *msi_desc = irq_data_get_msi_desc(data);
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struct irq_cfg *cfg = irqd_cfg(data);
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struct hv_retarget_device_interrupt *params;
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struct hv_pcibus_device *hbus;
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struct cpumask *dest;
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@ -1246,7 +1270,7 @@ static void hv_irq_unmask(struct irq_data *data)
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(hbus->hdev->dev_instance.b[7] << 8) |
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(hbus->hdev->dev_instance.b[6] & 0xf8) |
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PCI_FUNC(pdev->devfn);
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params->int_target.vector = cfg->vector;
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params->int_target.vector = hv_msi_get_int_vector(data);
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/*
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* Honoring apic->delivery_mode set to APIC_DELIVERY_MODE_FIXED by
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@ -1347,7 +1371,7 @@ static u32 hv_compose_msi_req_v1(
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int_pkt->wslot.slot = slot;
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int_pkt->int_desc.vector = vector;
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int_pkt->int_desc.vector_count = 1;
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int_pkt->int_desc.delivery_mode = APIC_DELIVERY_MODE_FIXED;
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int_pkt->int_desc.delivery_mode = DELIVERY_MODE;
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/*
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* Create MSI w/ dummy vCPU set, overwritten by subsequent retarget in
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@ -1377,7 +1401,7 @@ static u32 hv_compose_msi_req_v2(
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int_pkt->wslot.slot = slot;
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int_pkt->int_desc.vector = vector;
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int_pkt->int_desc.vector_count = 1;
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int_pkt->int_desc.delivery_mode = APIC_DELIVERY_MODE_FIXED;
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int_pkt->int_desc.delivery_mode = DELIVERY_MODE;
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cpu = hv_compose_msi_req_get_cpu(affinity);
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int_pkt->int_desc.processor_array[0] =
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hv_cpu_number_to_vp_number(cpu);
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@ -1397,7 +1421,7 @@ static u32 hv_compose_msi_req_v3(
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int_pkt->int_desc.vector = vector;
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int_pkt->int_desc.reserved = 0;
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int_pkt->int_desc.vector_count = 1;
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int_pkt->int_desc.delivery_mode = APIC_DELIVERY_MODE_FIXED;
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int_pkt->int_desc.delivery_mode = DELIVERY_MODE;
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cpu = hv_compose_msi_req_get_cpu(affinity);
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int_pkt->int_desc.processor_array[0] =
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hv_cpu_number_to_vp_number(cpu);
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@ -1419,7 +1443,6 @@ static u32 hv_compose_msi_req_v3(
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*/
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static void hv_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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struct irq_cfg *cfg = irqd_cfg(data);
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struct hv_pcibus_device *hbus;
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struct vmbus_channel *channel;
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struct hv_pci_dev *hpdev;
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@ -1470,7 +1493,7 @@ static void hv_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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size = hv_compose_msi_req_v1(&ctxt.int_pkts.v1,
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dest,
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hpdev->desc.win_slot.slot,
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cfg->vector);
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hv_msi_get_int_vector(data));
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break;
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case PCI_PROTOCOL_VERSION_1_2:
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@ -1478,14 +1501,14 @@ static void hv_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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size = hv_compose_msi_req_v2(&ctxt.int_pkts.v2,
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dest,
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hpdev->desc.win_slot.slot,
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cfg->vector);
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hv_msi_get_int_vector(data));
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break;
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case PCI_PROTOCOL_VERSION_1_4:
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size = hv_compose_msi_req_v3(&ctxt.int_pkts.v3,
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dest,
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hpdev->desc.win_slot.slot,
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cfg->vector);
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hv_msi_get_int_vector(data));
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break;
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default:
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@ -1594,14 +1617,14 @@ return_null_message:
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static struct irq_chip hv_msi_irq_chip = {
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.name = "Hyper-V PCIe MSI",
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.irq_compose_msi_msg = hv_compose_msi_msg,
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.irq_set_affinity = hv_set_affinity,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_ack = irq_chip_ack_parent,
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.irq_mask = hv_irq_mask,
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.irq_unmask = hv_irq_unmask,
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};
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static struct msi_domain_ops hv_msi_ops = {
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.msi_prepare = pci_msi_prepare,
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.msi_prepare = hv_msi_prepare,
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.msi_free = hv_msi_free,
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};
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@ -1625,12 +1648,12 @@ static int hv_pcie_init_irq_domain(struct hv_pcibus_device *hbus)
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hbus->msi_info.flags = (MSI_FLAG_USE_DEF_DOM_OPS |
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MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_MULTI_PCI_MSI |
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MSI_FLAG_PCI_MSIX);
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hbus->msi_info.handler = handle_edge_irq;
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hbus->msi_info.handler_name = "edge";
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hbus->msi_info.handler = FLOW_HANDLER;
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hbus->msi_info.handler_name = FLOW_NAME;
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hbus->msi_info.data = hbus;
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hbus->irq_domain = pci_msi_create_irq_domain(hbus->fwnode,
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&hbus->msi_info,
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x86_vector_domain);
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hv_pci_get_root_domain());
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if (!hbus->irq_domain) {
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dev_err(&hbus->hdev->device,
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"Failed to build an MSI IRQ domain\n");
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@ -3542,9 +3565,15 @@ static void __exit exit_hv_pci_drv(void)
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static int __init init_hv_pci_drv(void)
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{
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int ret;
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if (!hv_is_hyperv_initialized())
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return -ENODEV;
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ret = hv_pci_irqchip_init();
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if (ret)
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return ret;
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/* Set the invalid domain number's bit, so it will not be used */
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set_bit(HVPCI_DOM_INVALID, hvpci_dom_map);
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@ -540,39 +540,6 @@ enum hv_interrupt_source {
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HV_INTERRUPT_SOURCE_IOAPIC,
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};
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union hv_msi_address_register {
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u32 as_uint32;
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struct {
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u32 reserved1:2;
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u32 destination_mode:1;
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u32 redirection_hint:1;
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u32 reserved2:8;
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u32 destination_id:8;
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u32 msi_base:12;
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};
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} __packed;
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union hv_msi_data_register {
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u32 as_uint32;
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struct {
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u32 vector:8;
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u32 delivery_mode:3;
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u32 reserved1:3;
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u32 level_assert:1;
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u32 trigger_mode:1;
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u32 reserved2:16;
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};
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} __packed;
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/* HvRetargetDeviceInterrupt hypercall */
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union hv_msi_entry {
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u64 as_uint64;
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struct {
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union hv_msi_address_register address;
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union hv_msi_data_register data;
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} __packed;
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};
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union hv_ioapic_rte {
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u64 as_uint64;
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