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media: ti-vpe: cal: Group CAMERARX-related functions together
Group the CAMERARX functions together to make the overall driver structure easier to navigate. This only moves functions around, no functional change is included. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Benoit Parrot <bparrot@ti.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Laurent Pinchart
Mauro Carvalho Chehab
parent
f7cd15eb0b
commit
825800dc22
@ -468,9 +468,30 @@ static inline void set_field(u32 *valp, u32 field, u32 mask)
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*valp = val;
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}
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static u32 cal_camerarx_max_lanes(struct cal_camerarx *phy)
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static void cal_quickdump_regs(struct cal_dev *cal)
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{
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return phy->cal->data->camerarx[phy->instance].num_lanes;
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cal_info(cal, "CAL Registers @ 0x%pa:\n", &cal->res->start);
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print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
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(__force const void *)cal->base,
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resource_size(cal->res), false);
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if (cal->ctx[0]) {
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cal_info(cal, "CSI2 Core 0 Registers @ %pa:\n",
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&cal->ctx[0]->phy->res->start);
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print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
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(__force const void *)cal->ctx[0]->phy->base,
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resource_size(cal->ctx[0]->phy->res),
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false);
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}
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if (cal->ctx[1]) {
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cal_info(cal, "CSI2 Core 1 Registers @ %pa:\n",
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&cal->ctx[1]->phy->res->start);
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print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
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(__force const void *)cal->ctx[1]->phy->base,
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resource_size(cal->ctx[1]->phy->res),
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false);
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}
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}
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static u32 cal_data_get_num_csi2_phy(struct cal_dev *cal)
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@ -478,74 +499,16 @@ static u32 cal_data_get_num_csi2_phy(struct cal_dev *cal)
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return cal->data->num_csi2_phy;
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}
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static int cal_camerarx_regmap_init(struct cal_dev *cal,
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struct cal_camerarx *phy)
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{
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const struct cal_camerarx_data *phy_data;
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unsigned int i;
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if (!cal->data)
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return -EINVAL;
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phy_data = &cal->data->camerarx[phy->instance];
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for (i = 0; i < F_MAX_FIELDS; i++) {
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struct reg_field field = {
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.reg = cal->syscon_camerrx_offset,
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.lsb = phy_data->fields[i].lsb,
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.msb = phy_data->fields[i].msb,
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};
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/*
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* Here we update the reg offset with the
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* value found in DT
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*/
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phy->fields[i] = devm_regmap_field_alloc(&cal->pdev->dev,
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cal->syscon_camerrx,
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field);
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if (IS_ERR(phy->fields[i])) {
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cal_err(cal, "Unable to allocate regmap fields\n");
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return PTR_ERR(phy->fields[i]);
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}
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}
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return 0;
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}
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static struct regmap *cal_get_camerarx_regmap(struct cal_dev *cal)
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{
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struct platform_device *pdev = cal->pdev;
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struct regmap_config config = { };
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struct regmap *regmap;
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void __iomem *base;
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struct resource *res;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"camerrx_control");
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base)) {
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cal_err(cal, "failed to ioremap\n");
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return ERR_CAST(base);
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}
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cal_dbg(1, cal, "ioresource %s at %pa - %pa\n",
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res->name, &res->start, &res->end);
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config.reg_bits = 32;
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config.reg_stride = 4;
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config.val_bits = 32;
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config.max_register = resource_size(res) - 4;
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regmap = regmap_init_mmio(NULL, base, &config);
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if (IS_ERR(regmap))
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pr_err("regmap init failed\n");
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return regmap;
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}
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/*
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* Control Module CAMERARX block access
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/* ------------------------------------------------------------------
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* CAMERARX Management
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* ------------------------------------------------------------------
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*/
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static u32 cal_camerarx_max_lanes(struct cal_camerarx *phy)
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{
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return phy->cal->data->camerarx[phy->instance].num_lanes;
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}
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static void cal_camerarx_enable(struct cal_camerarx *phy)
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{
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u32 max_lanes;
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@ -565,61 +528,6 @@ static void cal_camerarx_disable(struct cal_camerarx *phy)
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regmap_field_write(phy->fields[F_CTRLCLKEN], 0);
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}
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/*
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* Camera Instance access block
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*/
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static struct cal_camerarx *cal_camerarx_create(struct cal_dev *cal,
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unsigned int instance)
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{
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struct platform_device *pdev = cal->pdev;
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struct cal_camerarx *phy;
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int ret;
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phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
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if (!phy)
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return ERR_PTR(-ENOMEM);
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phy->cal = cal;
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phy->instance = instance;
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phy->external_rate = 192000000;
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phy->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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(instance == 0) ?
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"cal_rx_core0" :
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"cal_rx_core1");
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phy->base = devm_ioremap_resource(&pdev->dev, phy->res);
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if (IS_ERR(phy->base)) {
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cal_err(cal, "failed to ioremap\n");
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return ERR_CAST(phy->base);
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}
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cal_dbg(1, cal, "ioresource %s at %pa - %pa\n",
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phy->res->name, &phy->res->start, &phy->res->end);
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ret = cal_camerarx_regmap_init(cal, phy);
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if (ret)
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return ERR_PTR(ret);
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return phy;
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}
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/*
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* Get Revision and HW info
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*/
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static void cal_get_hwinfo(struct cal_dev *cal)
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{
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u32 revision;
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u32 hwinfo;
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revision = reg_read(cal, CAL_HL_REVISION);
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cal_dbg(3, cal, "CAL_HL_REVISION = 0x%08x (expecting 0x40000200)\n",
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revision);
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hwinfo = reg_read(cal, CAL_HL_HWINFO);
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cal_dbg(3, cal, "CAL_HL_HWINFO = 0x%08x (expecting 0xA3C90469)\n",
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hwinfo);
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}
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/*
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* Errata i913: CSI2 LDO Needs to be disabled when module is powered on
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*
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@ -649,32 +557,6 @@ static void cal_camerarx_i913_errata(struct cal_camerarx *phy)
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reg_write(phy, CAL_CSI2_PHY_REG10, reg10);
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}
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static void cal_quickdump_regs(struct cal_dev *cal)
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{
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cal_info(cal, "CAL Registers @ 0x%pa:\n", &cal->res->start);
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print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
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(__force const void *)cal->base,
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resource_size(cal->res), false);
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if (cal->ctx[0]) {
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cal_info(cal, "CSI2 Core 0 Registers @ %pa:\n",
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&cal->ctx[0]->phy->res->start);
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print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
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(__force const void *)cal->ctx[0]->phy->base,
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resource_size(cal->ctx[0]->phy->res),
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false);
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}
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if (cal->ctx[1]) {
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cal_info(cal, "CSI2 Core 1 Registers @ %pa:\n",
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&cal->ctx[1]->phy->res->start);
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print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
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(__force const void *)cal->ctx[1]->phy->base,
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resource_size(cal->ctx[1]->phy->res),
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false);
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}
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}
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/*
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* Enable the expected IRQ sources
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*/
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@ -1010,6 +892,126 @@ static void cal_camerarx_ppi_disable(struct cal_camerarx *phy)
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0, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
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}
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static int cal_camerarx_get_external_info(struct cal_camerarx *phy)
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{
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struct v4l2_ctrl *ctrl;
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if (!phy->sensor)
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return -ENODEV;
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ctrl = v4l2_ctrl_find(phy->sensor->ctrl_handler, V4L2_CID_PIXEL_RATE);
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if (!ctrl) {
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phy_err(phy, "no pixel rate control in subdev: %s\n",
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phy->sensor->name);
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return -EPIPE;
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}
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phy->external_rate = v4l2_ctrl_g_ctrl_int64(ctrl);
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phy_dbg(3, phy, "sensor Pixel Rate: %u\n", phy->external_rate);
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return 0;
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}
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static int cal_camerarx_regmap_init(struct cal_dev *cal,
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struct cal_camerarx *phy)
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{
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const struct cal_camerarx_data *phy_data;
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unsigned int i;
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if (!cal->data)
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return -EINVAL;
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phy_data = &cal->data->camerarx[phy->instance];
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for (i = 0; i < F_MAX_FIELDS; i++) {
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struct reg_field field = {
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.reg = cal->syscon_camerrx_offset,
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.lsb = phy_data->fields[i].lsb,
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.msb = phy_data->fields[i].msb,
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};
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/*
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* Here we update the reg offset with the
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* value found in DT
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*/
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phy->fields[i] = devm_regmap_field_alloc(&cal->pdev->dev,
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cal->syscon_camerrx,
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field);
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if (IS_ERR(phy->fields[i])) {
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cal_err(cal, "Unable to allocate regmap fields\n");
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return PTR_ERR(phy->fields[i]);
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}
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}
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return 0;
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}
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static struct cal_camerarx *cal_camerarx_create(struct cal_dev *cal,
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unsigned int instance)
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{
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struct platform_device *pdev = cal->pdev;
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struct cal_camerarx *phy;
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int ret;
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phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
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if (!phy)
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return ERR_PTR(-ENOMEM);
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phy->cal = cal;
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phy->instance = instance;
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phy->external_rate = 192000000;
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phy->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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(instance == 0) ?
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"cal_rx_core0" :
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"cal_rx_core1");
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phy->base = devm_ioremap_resource(&pdev->dev, phy->res);
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if (IS_ERR(phy->base)) {
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cal_err(cal, "failed to ioremap\n");
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return ERR_CAST(phy->base);
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}
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cal_dbg(1, cal, "ioresource %s at %pa - %pa\n",
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phy->res->name, &phy->res->start, &phy->res->end);
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ret = cal_camerarx_regmap_init(cal, phy);
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if (ret)
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return ERR_PTR(ret);
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return phy;
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}
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static struct regmap *cal_get_camerarx_regmap(struct cal_dev *cal)
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{
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struct platform_device *pdev = cal->pdev;
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struct regmap_config config = { };
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struct regmap *regmap;
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void __iomem *base;
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struct resource *res;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"camerrx_control");
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base)) {
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cal_err(cal, "failed to ioremap\n");
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return ERR_CAST(base);
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}
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cal_dbg(1, cal, "ioresource %s at %pa - %pa\n",
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res->name, &res->start, &res->end);
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config.reg_bits = 32;
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config.reg_stride = 4;
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config.val_bits = 32;
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config.max_register = resource_size(res) - 4;
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regmap = regmap_init_mmio(NULL, base, &config);
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if (IS_ERR(regmap))
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pr_err("regmap init failed\n");
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return regmap;
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}
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static void csi2_ctx_config(struct cal_ctx *ctx)
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{
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u32 val;
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@ -1146,26 +1148,6 @@ static void cal_wr_dma_addr(struct cal_ctx *ctx, unsigned int dmaaddr)
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reg_write(ctx->cal, CAL_WR_DMA_ADDR(ctx->csi2_port), dmaaddr);
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}
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static int cal_camerarx_get_external_info(struct cal_camerarx *phy)
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{
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struct v4l2_ctrl *ctrl;
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if (!phy->sensor)
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return -ENODEV;
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ctrl = v4l2_ctrl_find(phy->sensor->ctrl_handler, V4L2_CID_PIXEL_RATE);
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if (!ctrl) {
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phy_err(phy, "no pixel rate control in subdev: %s\n",
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phy->sensor->name);
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return -EPIPE;
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}
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phy->external_rate = v4l2_ctrl_g_ctrl_int64(ctrl);
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phy_dbg(3, phy, "sensor Pixel Rate: %u\n", phy->external_rate);
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return 0;
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}
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static inline void cal_schedule_next_buffer(struct cal_ctx *ctx)
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{
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struct cal_dmaqueue *dma_q = &ctx->vidq;
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@ -2244,6 +2226,23 @@ static const struct of_device_id cal_of_match[] = {
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};
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MODULE_DEVICE_TABLE(of, cal_of_match);
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/*
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* Get Revision and HW info
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*/
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static void cal_get_hwinfo(struct cal_dev *cal)
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{
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u32 revision;
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u32 hwinfo;
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revision = reg_read(cal, CAL_HL_REVISION);
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cal_dbg(3, cal, "CAL_HL_REVISION = 0x%08x (expecting 0x40000200)\n",
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revision);
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hwinfo = reg_read(cal, CAL_HL_HWINFO);
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cal_dbg(3, cal, "CAL_HL_HWINFO = 0x%08x (expecting 0xA3C90469)\n",
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hwinfo);
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}
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static int cal_probe(struct platform_device *pdev)
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{
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struct cal_dev *cal;
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