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i2c: designware: Manually set RESTART bit between messages
If both IC_EMPTYFIFO_HOLD_MASTER_EN and IC_RESTART_EN are set to 1, the Designware I2C controller doesn't generate RESTART unless user specifically requests it by setting RESTART bit in IC_DATA_CMD register. Since IC_EMPTYFIFO_HOLD_MASTER_EN setting can't be detected from hardware register, we must always manually set the restart bit between messages. Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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@ -416,6 +416,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
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u32 addr = msgs[dev->msg_write_idx].addr;
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u32 addr = msgs[dev->msg_write_idx].addr;
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u32 buf_len = dev->tx_buf_len;
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u32 buf_len = dev->tx_buf_len;
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u8 *buf = dev->tx_buf;
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u8 *buf = dev->tx_buf;
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bool need_restart = false;
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intr_mask = DW_IC_INTR_DEFAULT_MASK;
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intr_mask = DW_IC_INTR_DEFAULT_MASK;
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@ -443,6 +444,14 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
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/* new i2c_msg */
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/* new i2c_msg */
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buf = msgs[dev->msg_write_idx].buf;
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buf = msgs[dev->msg_write_idx].buf;
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buf_len = msgs[dev->msg_write_idx].len;
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buf_len = msgs[dev->msg_write_idx].len;
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/* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
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* IC_RESTART_EN are set, we must manually
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* set restart bit between messages.
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*/
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if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
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(dev->msg_write_idx > 0))
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need_restart = true;
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}
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}
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tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
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tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
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@ -461,6 +470,11 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
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buf_len == 1)
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buf_len == 1)
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cmd |= BIT(9);
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cmd |= BIT(9);
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if (need_restart) {
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cmd |= BIT(10);
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need_restart = false;
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}
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if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
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if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
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/* avoid rx buffer overrun */
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/* avoid rx buffer overrun */
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