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spi: cadence: Change cs property reading.

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In current implementation cs property can be read only from
device-tree(for_each_available_child_of_node_scoped). Change it to fwnode
based read to allow property reading in ACPI case too.

Signed-off-by: Witold Sadowski <wsadowski@marvell.com>
Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
Link: https://patch.msgid.link/20240724154739.582367-9-wsadowski@marvell.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Witold Sadowski 2024-07-24 08:47:38 -07:00 committed by Mark Brown
parent 4b8cb7dcd8
commit 8232f1e258
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GPG Key ID: 24D68B725D5487D0
1 changed files with 8 additions and 3 deletions
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11
drivers/spi/spi-cadence-xspi.c
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@ -837,15 +837,20 @@ static irqreturn_t cdns_xspi_irq_handler(int this_irq, void *dev)
static int cdns_xspi_of_get_plat_data(struct platform_device *pdev)
{
struct device_node *node_prop = pdev->dev.of_node;
struct fwnode_handle *fwnode_child;
unsigned int cs;
for_each_available_child_of_node_scoped(node_prop, node_child) {
if (of_property_read_u32(node_child, "reg", &cs)) {
device_for_each_child_node(&pdev->dev, fwnode_child) {
if (!fwnode_device_is_available(fwnode_child))
continue;
if (fwnode_property_read_u32(fwnode_child, "reg", &cs)) {
dev_err(&pdev->dev, "Couldn't get memory chip select\n");
fwnode_handle_put(fwnode_child);
return -ENXIO;
} else if (cs >= CDNS_XSPI_MAX_BANKS) {
dev_err(&pdev->dev, "reg (cs) parameter value too large\n");
fwnode_handle_put(fwnode_child);
return -ENXIO;
}
}