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usb: phy: omap-usb3: updated dpll M,N values to support DRA7xx devices
Addition of the M and N recommended values for the USB3 PHY DPLL. Sysclk for DRA7xx is 20MHz. This yields: Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz Signed-off-by: Ruchika Kharwar <ruchika@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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@ -27,7 +27,7 @@
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#include <linux/delay.h>
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#include <linux/usb/omap_control_usb.h>
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#define NUM_SYS_CLKS 5
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#define NUM_SYS_CLKS 6
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#define PLL_STATUS 0x00000004
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#define PLL_GO 0x00000008
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#define PLL_CONFIGURATION1 0x0000000C
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@ -62,6 +62,7 @@ enum sys_clk_rate {
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CLK_RATE_12MHZ,
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CLK_RATE_16MHZ,
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CLK_RATE_19MHZ,
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CLK_RATE_20MHZ,
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CLK_RATE_26MHZ,
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CLK_RATE_38MHZ
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};
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@ -72,6 +73,8 @@ static struct usb_dpll_params omap_usb3_dpll_params[NUM_SYS_CLKS] = {
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{1172, 8, 4, 20, 65537}, /* 19.2 MHz */
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{1250, 12, 4, 20, 0}, /* 26 MHz */
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{3125, 47, 4, 20, 92843}, /* 38.4 MHz */
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{1000, 7, 4, 10, 0}, /* 20 MHz */
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};
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static int omap_usb3_suspend(struct usb_phy *x, int suspend)
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@ -122,6 +125,8 @@ static inline enum sys_clk_rate __get_sys_clk_index(unsigned long rate)
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return CLK_RATE_16MHZ;
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case 19200000:
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return CLK_RATE_19MHZ;
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case 20000000:
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return CLK_RATE_20MHZ;
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case 26000000:
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return CLK_RATE_26MHZ;
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case 38400000:
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