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drm/amdgpu: add amdgpu uapi header (v4)
This header defines the ioctl interface to the driver. v2: remove stale tiling defines v3: add appropriate padding v4: remove executable bits on header Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
c481a6802e
commit
81629cba1f
590
include/uapi/drm/amdgpu_drm.h
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590
include/uapi/drm/amdgpu_drm.h
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@ -0,0 +1,590 @@
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/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
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*
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* Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
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* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
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* Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Kevin E. Martin <martin@valinux.com>
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* Gareth Hughes <gareth@valinux.com>
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* Keith Whitwell <keith@tungstengraphics.com>
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*/
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#ifndef __AMDGPU_DRM_H__
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#define __AMDGPU_DRM_H__
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#include <drm/drm.h>
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#define DRM_AMDGPU_GEM_CREATE 0x00
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#define DRM_AMDGPU_GEM_MMAP 0x01
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#define DRM_AMDGPU_CTX 0x02
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#define DRM_AMDGPU_BO_LIST 0x03
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#define DRM_AMDGPU_CS 0x04
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#define DRM_AMDGPU_INFO 0x05
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#define DRM_AMDGPU_GEM_METADATA 0x06
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#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
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#define DRM_AMDGPU_GEM_VA 0x08
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#define DRM_AMDGPU_WAIT_CS 0x09
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#define DRM_AMDGPU_GEM_OP 0x10
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#define DRM_AMDGPU_GEM_USERPTR 0x11
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#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
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#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
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#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
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#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
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#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
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#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
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#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
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#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
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#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, union drm_amdgpu_gem_va)
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#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
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#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
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#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
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#define AMDGPU_GEM_DOMAIN_CPU 0x1
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#define AMDGPU_GEM_DOMAIN_GTT 0x2
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#define AMDGPU_GEM_DOMAIN_VRAM 0x4
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#define AMDGPU_GEM_DOMAIN_GDS 0x8
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#define AMDGPU_GEM_DOMAIN_GWS 0x10
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#define AMDGPU_GEM_DOMAIN_OA 0x20
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#define AMDGPU_GEM_DOMAIN_MASK 0x3F
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/* Flag that CPU access will be required for the case of VRAM domain */
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#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
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/* Flag that CPU access will not work, this VRAM domain is invisible */
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#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
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/* Flag that un-cached attributes should be used for GTT */
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#define AMDGPU_GEM_CREATE_CPU_GTT_UC (1 << 2)
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/* Flag that USWC attributes should be used for GTT */
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#define AMDGPU_GEM_CREATE_CPU_GTT_WC (1 << 3)
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/* Flag mask for GTT domain_flags */
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#define AMDGPU_GEM_CREATE_CPU_GTT_MASK \
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(AMDGPU_GEM_CREATE_CPU_GTT_WC | \
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AMDGPU_GEM_CREATE_CPU_GTT_UC | \
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AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | \
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AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
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struct drm_amdgpu_gem_create_in {
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/** the requested memory size */
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uint64_t bo_size;
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/** physical start_addr alignment in bytes for some HW requirements */
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uint64_t alignment;
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/** the requested memory domains */
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uint64_t domains;
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/** allocation flags */
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uint64_t domain_flags;
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};
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struct drm_amdgpu_gem_create_out {
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/** returned GEM object handle */
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uint32_t handle;
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uint32_t _pad;
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};
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union drm_amdgpu_gem_create {
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struct drm_amdgpu_gem_create_in in;
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struct drm_amdgpu_gem_create_out out;
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};
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/** Opcode to create new residency list. */
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#define AMDGPU_BO_LIST_OP_CREATE 0
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/** Opcode to destroy previously created residency list */
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#define AMDGPU_BO_LIST_OP_DESTROY 1
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/** Opcode to update resource information in the list */
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#define AMDGPU_BO_LIST_OP_UPDATE 2
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struct drm_amdgpu_bo_list_in {
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/** Type of operation */
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uint32_t operation;
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/** Handle of list or 0 if we want to create one */
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uint32_t list_handle;
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/** Number of BOs in list */
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uint32_t bo_number;
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/** Size of each element describing BO */
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uint32_t bo_info_size;
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/** Pointer to array describing BOs */
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uint64_t bo_info_ptr;
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};
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struct drm_amdgpu_bo_list_entry {
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/** Handle of BO */
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uint32_t bo_handle;
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/** New (if specified) BO priority to be used during migration */
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uint32_t bo_priority;
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};
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struct drm_amdgpu_bo_list_out {
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/** Handle of resource list */
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uint32_t list_handle;
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uint32_t _pad;
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};
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union drm_amdgpu_bo_list {
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struct drm_amdgpu_bo_list_in in;
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struct drm_amdgpu_bo_list_out out;
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};
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/* context related */
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#define AMDGPU_CTX_OP_ALLOC_CTX 1
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#define AMDGPU_CTX_OP_FREE_CTX 2
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#define AMDGPU_CTX_OP_QUERY_STATE 3
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#define AMDGPU_CTX_OP_STATE_RUNNING 1
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struct drm_amdgpu_ctx_in {
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uint32_t op;
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uint32_t flags;
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uint32_t ctx_id;
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uint32_t _pad;
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};
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union drm_amdgpu_ctx_out {
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struct {
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uint32_t ctx_id;
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uint32_t _pad;
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} alloc;
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struct {
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uint64_t flags;
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uint64_t hangs;
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} state;
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};
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union drm_amdgpu_ctx {
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struct drm_amdgpu_ctx_in in;
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union drm_amdgpu_ctx_out out;
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};
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/*
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* This is not a reliable API and you should expect it to fail for any
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* number of reasons and have fallback path that do not use userptr to
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* perform any operation.
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*/
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#define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
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#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
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#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
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#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
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struct drm_amdgpu_gem_userptr {
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uint64_t addr;
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uint64_t size;
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uint32_t flags;
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uint32_t handle;
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};
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#define AMDGPU_TILING_MACRO 0x1
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#define AMDGPU_TILING_MICRO 0x2
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#define AMDGPU_TILING_SWAP_16BIT 0x4
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#define AMDGPU_TILING_R600_NO_SCANOUT AMDGPU_TILING_SWAP_16BIT
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#define AMDGPU_TILING_SWAP_32BIT 0x8
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/* this object requires a surface when mapped - i.e. front buffer */
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#define AMDGPU_TILING_SURFACE 0x10
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#define AMDGPU_TILING_MICRO_SQUARE 0x20
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#define AMDGPU_TILING_EG_BANKW_SHIFT 8
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#define AMDGPU_TILING_EG_BANKW_MASK 0xf
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#define AMDGPU_TILING_EG_BANKH_SHIFT 12
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#define AMDGPU_TILING_EG_BANKH_MASK 0xf
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#define AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16
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#define AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf
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#define AMDGPU_TILING_EG_TILE_SPLIT_SHIFT 24
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#define AMDGPU_TILING_EG_TILE_SPLIT_MASK 0xf
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#define AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28
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#define AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
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#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
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#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
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/** The same structure is shared for input/output */
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struct drm_amdgpu_gem_metadata {
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uint32_t handle; /* GEM Object handle */
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uint32_t op; /** Do we want get or set metadata */
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struct {
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uint64_t flags;
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uint64_t tiling_info; /* family specific tiling info */
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uint32_t data_size_bytes;
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uint32_t data[64];
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} data;
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};
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struct drm_amdgpu_gem_mmap_in {
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uint32_t handle; /** the GEM object handle */
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uint32_t _pad;
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};
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struct drm_amdgpu_gem_mmap_out {
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uint64_t addr_ptr; /** mmap offset from the vma offset manager */
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};
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union drm_amdgpu_gem_mmap {
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struct drm_amdgpu_gem_mmap_in in;
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struct drm_amdgpu_gem_mmap_out out;
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};
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struct drm_amdgpu_gem_wait_idle_in {
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uint32_t handle; /* GEM object handle */
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uint32_t flags;
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uint64_t timeout; /* Timeout to wait. If 0 then returned immediately with the status */
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};
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struct drm_amdgpu_gem_wait_idle_out {
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uint32_t status; /* BO status: 0 - BO is idle, 1 - BO is busy */
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uint32_t domain; /* Returned current memory domain */
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};
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union drm_amdgpu_gem_wait_idle {
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struct drm_amdgpu_gem_wait_idle_in in;
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struct drm_amdgpu_gem_wait_idle_out out;
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};
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struct drm_amdgpu_wait_cs_in {
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uint64_t handle;
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uint64_t timeout;
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uint32_t ip_type;
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uint32_t ip_instance;
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uint32_t ring;
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uint32_t _pad;
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};
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struct drm_amdgpu_wait_cs_out {
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uint64_t status;
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};
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union drm_amdgpu_wait_cs {
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struct drm_amdgpu_wait_cs_in in;
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struct drm_amdgpu_wait_cs_out out;
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};
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/* Sets or returns a value associated with a buffer. */
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struct drm_amdgpu_gem_op {
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uint32_t handle; /* buffer */
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uint32_t op; /* AMDGPU_GEM_OP_* */
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uint64_t value; /* input or return value */
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};
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#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
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#define AMDGPU_GEM_OP_SET_INITIAL_DOMAIN 1
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#define AMDGPU_VA_OP_MAP 1
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#define AMDGPU_VA_OP_UNMAP 2
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#define AMDGPU_VA_RESULT_OK 0
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#define AMDGPU_VA_RESULT_ERROR 1
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#define AMDGPU_VA_RESULT_VA_INVALID_ALIGNMENT 2
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/* Mapping flags */
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/* readable mapping */
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#define AMDGPU_VM_PAGE_READABLE (1 << 1)
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/* writable mapping */
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#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
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/* executable mapping, new for VI */
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#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
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struct drm_amdgpu_gem_va_in {
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/* GEM object handle */
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uint32_t handle;
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uint32_t _pad;
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/* map or unmap*/
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uint32_t operation;
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/* specify mapping flags */
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uint32_t flags;
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/* va address to assign . Must be correctly aligned.*/
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uint64_t va_address;
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/* Specify offset inside of BO to assign. Must be correctly aligned.*/
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uint64_t offset_in_bo;
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/* Specify mapping size. If 0 and offset is 0 then map the whole BO.*/
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/* Must be correctly aligned. */
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uint64_t map_size;
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};
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struct drm_amdgpu_gem_va_out {
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uint32_t result;
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uint32_t _pad;
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};
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union drm_amdgpu_gem_va {
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struct drm_amdgpu_gem_va_in in;
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struct drm_amdgpu_gem_va_out out;
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};
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#define AMDGPU_HW_IP_GFX 0
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#define AMDGPU_HW_IP_COMPUTE 1
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#define AMDGPU_HW_IP_DMA 2
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#define AMDGPU_HW_IP_UVD 3
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#define AMDGPU_HW_IP_VCE 4
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#define AMDGPU_HW_IP_NUM 5
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#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
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#define AMDGPU_CHUNK_ID_IB 0x01
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#define AMDGPU_CHUNK_ID_FENCE 0x02
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struct drm_amdgpu_cs_chunk {
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uint32_t chunk_id;
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uint32_t length_dw;
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uint64_t chunk_data;
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};
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struct drm_amdgpu_cs_in {
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/** Rendering context id */
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uint32_t ctx_id;
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/** Handle of resource list associated with CS */
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uint32_t bo_list_handle;
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uint32_t num_chunks;
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uint32_t _pad;
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/* this points to uint64_t * which point to cs chunks */
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uint64_t chunks;
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};
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struct drm_amdgpu_cs_out {
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uint64_t handle;
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};
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union drm_amdgpu_cs {
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struct drm_amdgpu_cs_in in;
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struct drm_amdgpu_cs_out out;
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};
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/* Specify flags to be used for IB */
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/* This IB should be submitted to CE */
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#define AMDGPU_IB_FLAG_CE (1<<0)
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/* GDS is used by this IB */
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#define AMDGPU_IB_FLAG_GDS (1<<1)
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struct drm_amdgpu_cs_chunk_ib {
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/**
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* Handle of GEM object to be used as IB or 0 if it is already in
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* residency list.
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*/
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uint32_t handle;
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uint32_t flags; /* IB Flags */
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uint64_t va_start; /* Virtual address to begin IB execution */
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uint32_t ib_bytes; /* Size of submission */
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uint32_t ip_type; /* HW IP to submit to */
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uint32_t ip_instance; /* HW IP index of the same type to submit to */
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uint32_t ring; /* Ring index to submit to */
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};
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struct drm_amdgpu_cs_chunk_fence {
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uint32_t handle;
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uint32_t offset;
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};
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struct drm_amdgpu_cs_chunk_data {
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union {
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struct drm_amdgpu_cs_chunk_ib ib_data;
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struct drm_amdgpu_cs_chunk_fence fence_data;
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};
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};
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/**
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* Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
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*
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*/
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#define AMDGPU_IDS_FLAGS_FUSION 0x1
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/* indicate if acceleration can be working */
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#define AMDGPU_INFO_ACCEL_WORKING 0x00
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/* get the crtc_id from the mode object id? */
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#define AMDGPU_INFO_CRTC_FROM_ID 0x01
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/* query hw IP info */
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#define AMDGPU_INFO_HW_IP_INFO 0x02
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/* query hw IP instance count for the specified type */
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#define AMDGPU_INFO_HW_IP_COUNT 0x03
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/* timestamp for GL_ARB_timer_query */
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#define AMDGPU_INFO_TIMESTAMP 0x05
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||||
/* Query the firmware version */
|
||||
#define AMDGPU_INFO_FW_VERSION 0x0e
|
||||
/* Subquery id: Query VCE firmware version */
|
||||
#define AMDGPU_INFO_FW_VCE 0x1
|
||||
/* Subquery id: Query UVD firmware version */
|
||||
#define AMDGPU_INFO_FW_UVD 0x2
|
||||
/* Subquery id: Query GMC firmware version */
|
||||
#define AMDGPU_INFO_FW_GMC 0x03
|
||||
/* Subquery id: Query GFX ME firmware version */
|
||||
#define AMDGPU_INFO_FW_GFX_ME 0x04
|
||||
/* Subquery id: Query GFX PFP firmware version */
|
||||
#define AMDGPU_INFO_FW_GFX_PFP 0x05
|
||||
/* Subquery id: Query GFX CE firmware version */
|
||||
#define AMDGPU_INFO_FW_GFX_CE 0x06
|
||||
/* Subquery id: Query GFX RLC firmware version */
|
||||
#define AMDGPU_INFO_FW_GFX_RLC 0x07
|
||||
/* Subquery id: Query GFX MEC firmware version */
|
||||
#define AMDGPU_INFO_FW_GFX_MEC 0x08
|
||||
/* Subquery id: Query SMC firmware version */
|
||||
#define AMDGPU_INFO_FW_SMC 0x0a
|
||||
/* Subquery id: Query SDMA firmware version */
|
||||
#define AMDGPU_INFO_FW_SDMA 0x0b
|
||||
/* number of bytes moved for TTM migration */
|
||||
#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
|
||||
/* the used VRAM size */
|
||||
#define AMDGPU_INFO_VRAM_USAGE 0x10
|
||||
/* the used GTT size */
|
||||
#define AMDGPU_INFO_GTT_USAGE 0x11
|
||||
/* Information about GDS, etc. resource configuration */
|
||||
#define AMDGPU_INFO_GDS_CONFIG 0x13
|
||||
/* Query information about VRAM and GTT domains */
|
||||
#define AMDGPU_INFO_VRAM_GTT 0x14
|
||||
/* Query information about register in MMR address space*/
|
||||
#define AMDGPU_INFO_READ_MMR_REG 0x15
|
||||
/* Query information about device: rev id, family, etc. */
|
||||
#define AMDGPU_INFO_DEV_INFO 0x16
|
||||
/* visible vram usage */
|
||||
#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
|
||||
|
||||
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
|
||||
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
|
||||
#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
|
||||
#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
|
||||
|
||||
/* Input structure for the INFO ioctl */
|
||||
struct drm_amdgpu_info {
|
||||
/* Where the return value will be stored */
|
||||
uint64_t return_pointer;
|
||||
/* The size of the return value. Just like "size" in "snprintf",
|
||||
* it limits how many bytes the kernel can write. */
|
||||
uint32_t return_size;
|
||||
/* The query request id. */
|
||||
uint32_t query;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t id;
|
||||
uint32_t _pad;
|
||||
} mode_crtc;
|
||||
|
||||
struct {
|
||||
/** AMDGPU_HW_IP_* */
|
||||
uint32_t type;
|
||||
/**
|
||||
* Index of the IP if there are more IPs of the same type.
|
||||
* Ignored by AMDGPU_INFO_HW_IP_COUNT.
|
||||
*/
|
||||
uint32_t ip_instance;
|
||||
} query_hw_ip;
|
||||
|
||||
struct {
|
||||
uint32_t dword_offset;
|
||||
uint32_t count; /* number of registers to read */
|
||||
uint32_t instance;
|
||||
uint32_t flags;
|
||||
} read_mmr_reg;
|
||||
|
||||
struct {
|
||||
/** AMDGPU_INFO_FW_* */
|
||||
uint32_t fw_type;
|
||||
/** Index of the IP if there are more IPs of the same type. */
|
||||
uint32_t ip_instance;
|
||||
/**
|
||||
* Index of the engine. Whether this is used depends
|
||||
* on the firmware type. (e.g. MEC, SDMA)
|
||||
*/
|
||||
uint32_t index;
|
||||
uint32_t _pad;
|
||||
} query_fw;
|
||||
};
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_gds {
|
||||
/** GDS GFX partition size */
|
||||
uint32_t gds_gfx_partition_size;
|
||||
/** GDS compute partition size */
|
||||
uint32_t compute_partition_size;
|
||||
/** total GDS memory size */
|
||||
uint32_t gds_total_size;
|
||||
/** GWS size per GFX partition */
|
||||
uint32_t gws_per_gfx_partition;
|
||||
/** GSW size per compute partition */
|
||||
uint32_t gws_per_compute_partition;
|
||||
/** OA size per GFX partition */
|
||||
uint32_t oa_per_gfx_partition;
|
||||
/** OA size per compute partition */
|
||||
uint32_t oa_per_compute_partition;
|
||||
uint32_t _pad;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_vram_gtt {
|
||||
uint64_t vram_size;
|
||||
uint64_t vram_cpu_accessible_size;
|
||||
uint64_t gtt_size;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_firmware {
|
||||
uint32_t ver;
|
||||
uint32_t feature;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_device {
|
||||
/** PCI Device ID */
|
||||
uint32_t device_id;
|
||||
/** Internal chip revision: A0, A1, etc.) */
|
||||
uint32_t chip_rev;
|
||||
uint32_t external_rev;
|
||||
/** Revision id in PCI Config space */
|
||||
uint32_t pci_rev;
|
||||
uint32_t family;
|
||||
uint32_t num_shader_engines;
|
||||
uint32_t num_shader_arrays_per_engine;
|
||||
uint32_t gpu_counter_freq; /* in KHz */
|
||||
uint64_t max_engine_clock; /* in KHz */
|
||||
/* cu information */
|
||||
uint32_t cu_active_number;
|
||||
uint32_t cu_ao_mask;
|
||||
uint32_t cu_bitmap[4][4];
|
||||
/** Render backend pipe mask. One render backend is CB+DB. */
|
||||
uint32_t enabled_rb_pipes_mask;
|
||||
uint32_t num_rb_pipes;
|
||||
uint32_t num_hw_gfx_contexts;
|
||||
uint32_t _pad;
|
||||
uint64_t ids_flags;
|
||||
/** Starting virtual address for UMDs. */
|
||||
uint64_t virtual_address_offset;
|
||||
/** Required alignment of virtual addresses. */
|
||||
uint32_t virtual_address_alignment;
|
||||
/** Page table entry - fragment size */
|
||||
uint32_t pte_fragment_size;
|
||||
uint32_t gart_page_size;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_hw_ip {
|
||||
/** Version of h/w IP */
|
||||
uint32_t hw_ip_version_major;
|
||||
uint32_t hw_ip_version_minor;
|
||||
/** Capabilities */
|
||||
uint64_t capabilities_flags;
|
||||
/** Bitmask of available rings. Bit 0 means ring 0, etc. */
|
||||
uint32_t available_rings;
|
||||
uint32_t _pad;
|
||||
};
|
||||
|
||||
/*
|
||||
* Supported GPU families
|
||||
*/
|
||||
#define AMDGPU_FAMILY_UNKNOWN 0
|
||||
#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
|
||||
#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
|
||||
#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
|
||||
#define AMDGPU_FAMILY_CZ 135 /* Carrizo */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user