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dt-bindings: dw-apb-ictl: Update binding to describe use as primary interrupt controller

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Add the required updates to describe the use of dw-apb-ictl as a primary
interrupt controller.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
[maz: commit message]
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200924071754.4509-5-thunder.leizhen@huawei.com
This commit is contained in:
Zhen Lei 2020-09-24 15:17:52 +08:00 committed by Marc Zyngier
parent 54a38440b8
commit 8156b80fd4
1 changed files with 13 additions and 1 deletions
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14
Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
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@ -2,7 +2,8 @@ Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
Synopsys DesignWare provides interrupt controller IP for APB known as Synopsys DesignWare provides interrupt controller IP for APB known as
dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
APB bus, e.g. Marvell Armada 1500. APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
controller in some SoCs, e.g. Hisilicon SD5203.
Required properties: Required properties:
- compatible: shall be "snps,dw-apb-ictl" - compatible: shall be "snps,dw-apb-ictl"
@ -10,6 +11,8 @@ Required properties:
region starting with ENABLE_LOW register region starting with ENABLE_LOW register
- interrupt-controller: identifies the node as an interrupt controller - interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
Additional required property when it's used as secondary interrupt controller:
- interrupts: interrupt reference to primary interrupt controller - interrupts: interrupt reference to primary interrupt controller
The interrupt sources map to the corresponding bits in the interrupt The interrupt sources map to the corresponding bits in the interrupt
@ -21,6 +24,7 @@ registers, i.e.
- (optional) fast interrupts start at 64. - (optional) fast interrupts start at 64.
Example: Example:
/* dw_apb_ictl is used as secondary interrupt controller */
aic: interrupt-controller@3000 { aic: interrupt-controller@3000 {
compatible = "snps,dw-apb-ictl"; compatible = "snps,dw-apb-ictl";
reg = <0x3000 0xc00>; reg = <0x3000 0xc00>;
@ -29,3 +33,11 @@ Example:
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
}; };
/* dw_apb_ictl is used as primary interrupt controller */
vic: interrupt-controller@10130000 {
compatible = "snps,dw-apb-ictl";
reg = <0x10130000 0x1000>;
interrupt-controller;
#interrupt-cells = <1>;
};