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ASoC: pcm512x: Support mastering BCLK/LRCLK without using the PLL
Use register field names from the seemingly compatible PCM5242 datasheet, as the PCM512x and PCM514x datasheets are severly lacking. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Peter Rosin
Mark Brown
parent
376dc4903e
commit
8124930713
@ -23,6 +23,7 @@
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#include <linux/regulator/consumer.h>
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#include <sound/soc.h>
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#include <sound/soc-dapm.h>
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#include <sound/pcm_params.h>
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#include <sound/tlv.h>
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#include "pcm512x.h"
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@ -39,6 +40,7 @@ struct pcm512x_priv {
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struct clk *sclk;
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struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES];
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struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES];
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int fmt;
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};
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/*
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@ -69,6 +71,7 @@ static const struct reg_default pcm512x_reg_defaults[] = {
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{ PCM512x_MUTE, 0x00 },
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{ PCM512x_DSP, 0x00 },
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{ PCM512x_PLL_REF, 0x00 },
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{ PCM512x_DAC_REF, 0x00 },
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{ PCM512x_DAC_ROUTING, 0x11 },
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{ PCM512x_DSP_PROGRAM, 0x01 },
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{ PCM512x_CLKDET, 0x00 },
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@ -87,6 +90,18 @@ static const struct reg_default pcm512x_reg_defaults[] = {
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{ PCM512x_ANALOG_GAIN_BOOST, 0x00 },
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{ PCM512x_VCOM_CTRL_1, 0x00 },
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{ PCM512x_VCOM_CTRL_2, 0x01 },
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{ PCM512x_BCLK_LRCLK_CFG, 0x00 },
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{ PCM512x_MASTER_MODE, 0x7c },
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{ PCM512x_SYNCHRONIZE, 0x10 },
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{ PCM512x_DSP_CLKDIV, 0x00 },
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{ PCM512x_DAC_CLKDIV, 0x00 },
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{ PCM512x_NCP_CLKDIV, 0x00 },
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{ PCM512x_OSR_CLKDIV, 0x00 },
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{ PCM512x_MASTER_CLKDIV_1, 0x00 },
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{ PCM512x_MASTER_CLKDIV_2, 0x00 },
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{ PCM512x_FS_SPEED_MODE, 0x00 },
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{ PCM512x_IDAC_1, 0x01 },
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{ PCM512x_IDAC_2, 0x00 },
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};
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static bool pcm512x_readable(struct device *dev, unsigned int reg)
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@ -103,6 +118,8 @@ static bool pcm512x_readable(struct device *dev, unsigned int reg)
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case PCM512x_DSP_GPIO_INPUT:
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case PCM512x_MASTER_MODE:
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case PCM512x_PLL_REF:
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case PCM512x_DAC_REF:
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case PCM512x_SYNCHRONIZE:
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case PCM512x_PLL_COEFF_0:
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case PCM512x_PLL_COEFF_1:
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case PCM512x_PLL_COEFF_2:
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@ -303,6 +320,94 @@ static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = {
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{ "OUTR", NULL, "DACR" },
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};
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static const u32 pcm512x_dai_rates[] = {
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8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
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88200, 96000, 176400, 192000, 384000,
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};
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static const struct snd_pcm_hw_constraint_list constraints_slave = {
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.count = ARRAY_SIZE(pcm512x_dai_rates),
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.list = pcm512x_dai_rates,
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};
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static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_codec *codec = dai->codec;
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struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
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struct device *dev = dai->dev;
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struct snd_pcm_hw_constraint_ratnums *constraints_no_pll;
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struct snd_ratnum *rats_no_pll;
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if (IS_ERR(pcm512x->sclk)) {
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dev_err(dev, "Need SCLK for master mode: %ld\n",
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PTR_ERR(pcm512x->sclk));
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return PTR_ERR(pcm512x->sclk);
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}
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constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll),
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GFP_KERNEL);
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if (!constraints_no_pll)
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return -ENOMEM;
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constraints_no_pll->nrats = 1;
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rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL);
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if (!rats_no_pll)
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return -ENOMEM;
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constraints_no_pll->rats = rats_no_pll;
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rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;
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rats_no_pll->den_min = 1;
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rats_no_pll->den_max = 128;
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rats_no_pll->den_step = 1;
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return snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_RATE,
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constraints_no_pll);
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}
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static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_codec *codec = dai->codec;
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struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
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struct device *dev = dai->dev;
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struct regmap *regmap = pcm512x->regmap;
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if (IS_ERR(pcm512x->sclk)) {
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dev_info(dev, "No SCLK, using BCLK: %ld\n",
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PTR_ERR(pcm512x->sclk));
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/* Disable reporting of missing SCLK as an error */
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regmap_update_bits(regmap, PCM512x_ERROR_DETECT,
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PCM512x_IDCH, PCM512x_IDCH);
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/* Switch PLL input to BCLK */
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regmap_update_bits(regmap, PCM512x_PLL_REF,
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PCM512x_SREF, PCM512x_SREF_BCK);
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}
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return snd_pcm_hw_constraint_list(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_RATE,
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&constraints_slave);
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}
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static int pcm512x_dai_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_codec *codec = dai->codec;
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struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
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switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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return pcm512x_dai_startup_master(substream, dai);
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case SND_SOC_DAIFMT_CBS_CFS:
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return pcm512x_dai_startup_slave(substream, dai);
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default:
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return -EINVAL;
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}
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}
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static int pcm512x_set_bias_level(struct snd_soc_codec *codec,
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enum snd_soc_bias_level level)
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{
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@ -340,17 +445,333 @@ static int pcm512x_set_bias_level(struct snd_soc_codec *codec,
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return 0;
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}
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static int pcm512x_set_dividers(struct snd_soc_dai *dai,
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struct snd_pcm_hw_params *params)
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{
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struct device *dev = dai->dev;
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struct snd_soc_codec *codec = dai->codec;
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struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
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unsigned long sck_rate;
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unsigned long mck_rate;
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unsigned long bclk_rate;
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unsigned long sample_rate;
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unsigned long osr_rate;
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int bclk_div;
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int lrclk_div;
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int dsp_div;
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int dac_div;
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unsigned long dac_rate;
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int ncp_div;
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int osr_div;
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unsigned long dac_mul;
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unsigned long sck_mul;
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int ret;
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int idac;
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int fssp;
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lrclk_div = snd_soc_params_to_frame_size(params);
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if (lrclk_div == 0) {
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dev_err(dev, "No LRCLK?\n");
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return -EINVAL;
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}
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sck_rate = clk_get_rate(pcm512x->sclk);
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bclk_div = params->rate_den * 64 / lrclk_div;
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bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div);
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mck_rate = sck_rate;
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if (bclk_div > 128) {
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dev_err(dev, "Failed to find BCLK divider\n");
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return -EINVAL;
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}
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/* the actual rate */
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sample_rate = sck_rate / bclk_div / lrclk_div;
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osr_rate = 16 * sample_rate;
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/* run DSP no faster than 50 MHz */
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dsp_div = mck_rate > 50000000 ? 2 : 1;
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/* run DAC no faster than 6144000 Hz */
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dac_mul = 6144000 / osr_rate;
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sck_mul = sck_rate / osr_rate;
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for (; dac_mul; dac_mul--) {
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if (!(sck_mul % dac_mul))
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break;
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}
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if (!dac_mul) {
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dev_err(dev, "Failed to find DAC rate\n");
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return -EINVAL;
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}
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dac_rate = dac_mul * osr_rate;
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dev_dbg(dev, "dac_rate %lu sample_rate %lu\n", dac_rate, sample_rate);
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dac_div = DIV_ROUND_CLOSEST(sck_rate, dac_rate);
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if (dac_div > 128) {
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dev_err(dev, "Failed to find DAC divider\n");
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return -EINVAL;
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}
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ncp_div = DIV_ROUND_CLOSEST(sck_rate / dac_div, 1536000);
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if (ncp_div > 128 || sck_rate / dac_div / ncp_div > 2048000) {
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/* run NCP no faster than 2048000 Hz, but why? */
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ncp_div = DIV_ROUND_UP(sck_rate / dac_div, 2048000);
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if (ncp_div > 128) {
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dev_err(dev, "Failed to find NCP divider\n");
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return -EINVAL;
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}
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}
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osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate);
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if (osr_div > 128) {
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dev_err(dev, "Failed to find OSR divider\n");
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return -EINVAL;
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}
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idac = mck_rate / (dsp_div * sample_rate);
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ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1);
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if (ret != 0) {
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dev_err(dev, "Failed to write DSP divider: %d\n", ret);
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return ret;
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}
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ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1);
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if (ret != 0) {
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dev_err(dev, "Failed to write DAC divider: %d\n", ret);
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return ret;
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}
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ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1);
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if (ret != 0) {
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dev_err(dev, "Failed to write NCP divider: %d\n", ret);
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return ret;
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}
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ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1);
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if (ret != 0) {
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dev_err(dev, "Failed to write OSR divider: %d\n", ret);
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return ret;
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}
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ret = regmap_write(pcm512x->regmap,
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PCM512x_MASTER_CLKDIV_1, bclk_div - 1);
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if (ret != 0) {
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dev_err(dev, "Failed to write BCLK divider: %d\n", ret);
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return ret;
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}
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ret = regmap_write(pcm512x->regmap,
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PCM512x_MASTER_CLKDIV_2, lrclk_div - 1);
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if (ret != 0) {
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dev_err(dev, "Failed to write LRCLK divider: %d\n", ret);
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return ret;
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}
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ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8);
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if (ret != 0) {
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dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret);
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return ret;
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}
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ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff);
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if (ret != 0) {
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dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret);
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return ret;
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}
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if (sample_rate <= 48000)
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fssp = PCM512x_FSSP_48KHZ;
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else if (sample_rate <= 96000)
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fssp = PCM512x_FSSP_96KHZ;
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else if (sample_rate <= 192000)
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fssp = PCM512x_FSSP_192KHZ;
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else
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fssp = PCM512x_FSSP_384KHZ;
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ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE,
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PCM512x_FSSP, fssp);
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if (ret != 0) {
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dev_err(codec->dev, "Failed to set fs speed: %d\n", ret);
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return ret;
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}
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dev_dbg(codec->dev, "DSP divider %d\n", dsp_div);
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dev_dbg(codec->dev, "DAC divider %d\n", dac_div);
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dev_dbg(codec->dev, "NCP divider %d\n", ncp_div);
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dev_dbg(codec->dev, "OSR divider %d\n", osr_div);
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dev_dbg(codec->dev, "BCK divider %d\n", bclk_div);
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dev_dbg(codec->dev, "LRCK divider %d\n", lrclk_div);
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dev_dbg(codec->dev, "IDAC %d\n", idac);
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dev_dbg(codec->dev, "1<<FSSP %d\n", 1 << fssp);
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return 0;
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}
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static int pcm512x_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_codec *codec = dai->codec;
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struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
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int alen;
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int ret;
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dev_dbg(codec->dev, "hw_params %u Hz, %u channels\n",
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params_rate(params),
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params_channels(params));
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switch (snd_pcm_format_width(params_format(params))) {
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case 16:
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alen = PCM512x_ALEN_16;
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break;
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case 20:
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alen = PCM512x_ALEN_20;
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break;
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case 24:
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alen = PCM512x_ALEN_24;
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break;
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case 32:
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alen = PCM512x_ALEN_32;
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break;
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default:
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dev_err(codec->dev, "Bad frame size: %d\n",
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snd_pcm_format_width(params_format(params)));
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return -EINVAL;
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}
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switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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ret = regmap_update_bits(pcm512x->regmap,
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PCM512x_BCLK_LRCLK_CFG,
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PCM512x_BCKP
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| PCM512x_BCKO | PCM512x_LRKO,
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0);
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if (ret != 0) {
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dev_err(codec->dev,
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"Failed to enable slave mode: %d\n", ret);
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return ret;
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}
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ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
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PCM512x_DCAS, 0);
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if (ret != 0) {
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dev_err(codec->dev,
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"Failed to enable clock divider autoset: %d\n",
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ret);
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return ret;
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}
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return 0;
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case SND_SOC_DAIFMT_CBM_CFM:
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break;
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default:
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return -EINVAL;
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}
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ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1,
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PCM512x_ALEN, alen);
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if (ret != 0) {
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dev_err(codec->dev, "Failed to set frame size: %d\n", ret);
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return ret;
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}
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ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
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PCM512x_IDFS | PCM512x_IDBK
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| PCM512x_IDSK | PCM512x_IDCH
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| PCM512x_IDCM | PCM512x_DCAS
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| PCM512x_IPLK,
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PCM512x_IDFS | PCM512x_IDBK
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| PCM512x_IDSK | PCM512x_IDCH
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| PCM512x_DCAS | PCM512x_IPLK);
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if (ret != 0) {
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dev_err(codec->dev,
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"Failed to ignore auto-clock failures: %d\n",
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ret);
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return ret;
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}
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ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
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PCM512x_PLLE, 0);
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if (ret != 0) {
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dev_err(codec->dev, "Failed to disable pll: %d\n", ret);
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return ret;
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}
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ret = pcm512x_set_dividers(dai, params);
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if (ret != 0)
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return ret;
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ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
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PCM512x_SDAC, PCM512x_SDAC_SCK);
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if (ret != 0) {
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dev_err(codec->dev, "Failed to set sck as dacref: %d\n", ret);
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return ret;
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}
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ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG,
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PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO,
|
||||
PCM512x_BCKO | PCM512x_LRKO);
|
||||
if (ret != 0) {
|
||||
dev_err(codec->dev, "Failed to enable clock output: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE,
|
||||
PCM512x_RLRK | PCM512x_RBCK,
|
||||
PCM512x_RLRK | PCM512x_RBCK);
|
||||
if (ret != 0) {
|
||||
dev_err(codec->dev, "Failed to enable master mode: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
|
||||
PCM512x_RQSY, PCM512x_RQSY_HALT);
|
||||
if (ret != 0) {
|
||||
dev_err(codec->dev, "Failed to halt clocks: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
|
||||
PCM512x_RQSY, PCM512x_RQSY_RESUME);
|
||||
if (ret != 0) {
|
||||
dev_err(codec->dev, "Failed to resume clocks: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
|
||||
{
|
||||
struct snd_soc_codec *codec = dai->codec;
|
||||
struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
|
||||
|
||||
pcm512x->fmt = fmt;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct snd_soc_dai_ops pcm512x_dai_ops = {
|
||||
.startup = pcm512x_dai_startup,
|
||||
.hw_params = pcm512x_hw_params,
|
||||
.set_fmt = pcm512x_set_fmt,
|
||||
};
|
||||
|
||||
static struct snd_soc_dai_driver pcm512x_dai = {
|
||||
.name = "pcm512x-hifi",
|
||||
.playback = {
|
||||
.stream_name = "Playback",
|
||||
.channels_min = 2,
|
||||
.channels_max = 2,
|
||||
.rates = SNDRV_PCM_RATE_8000_192000,
|
||||
.rates = SNDRV_PCM_RATE_CONTINUOUS,
|
||||
.rate_min = 8000,
|
||||
.rate_max = 384000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE |
|
||||
SNDRV_PCM_FMTBIT_S24_LE |
|
||||
SNDRV_PCM_FMTBIT_S32_LE
|
||||
},
|
||||
.ops = &pcm512x_dai_ops,
|
||||
};
|
||||
|
||||
static struct snd_soc_codec_driver pcm512x_codec_driver = {
|
||||
@ -448,21 +869,9 @@ int pcm512x_probe(struct device *dev, struct regmap *regmap)
|
||||
}
|
||||
|
||||
pcm512x->sclk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(pcm512x->sclk)) {
|
||||
if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
dev_info(dev, "No SCLK, using BCLK: %ld\n",
|
||||
PTR_ERR(pcm512x->sclk));
|
||||
|
||||
/* Disable reporting of missing SCLK as an error */
|
||||
regmap_update_bits(regmap, PCM512x_ERROR_DETECT,
|
||||
PCM512x_IDCH, PCM512x_IDCH);
|
||||
|
||||
/* Switch PLL input to BCLK */
|
||||
regmap_update_bits(regmap, PCM512x_PLL_REF,
|
||||
PCM512x_SREF, PCM512x_SREF);
|
||||
} else {
|
||||
if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
if (!IS_ERR(pcm512x->sclk)) {
|
||||
ret = clk_prepare_enable(pcm512x->sclk);
|
||||
if (ret != 0) {
|
||||
dev_err(dev, "Failed to enable SCLK: %d\n", ret);
|
||||
|
||||
@ -37,6 +37,8 @@
|
||||
#define PCM512x_DSP_GPIO_INPUT (PCM512x_PAGE_BASE(0) + 10)
|
||||
#define PCM512x_MASTER_MODE (PCM512x_PAGE_BASE(0) + 12)
|
||||
#define PCM512x_PLL_REF (PCM512x_PAGE_BASE(0) + 13)
|
||||
#define PCM512x_DAC_REF (PCM512x_PAGE_BASE(0) + 14)
|
||||
#define PCM512x_SYNCHRONIZE (PCM512x_PAGE_BASE(0) + 19)
|
||||
#define PCM512x_PLL_COEFF_0 (PCM512x_PAGE_BASE(0) + 20)
|
||||
#define PCM512x_PLL_COEFF_1 (PCM512x_PAGE_BASE(0) + 21)
|
||||
#define PCM512x_PLL_COEFF_2 (PCM512x_PAGE_BASE(0) + 22)
|
||||
@ -119,8 +121,47 @@
|
||||
#define PCM512x_DEMP (1 << 4)
|
||||
#define PCM512x_DEMP_SHIFT 4
|
||||
|
||||
/* Page 0, Register 9 - BCK, LRCLK configuration */
|
||||
#define PCM512x_LRKO (1 << 0)
|
||||
#define PCM512x_LRKO_SHIFT 0
|
||||
#define PCM512x_BCKO (1 << 4)
|
||||
#define PCM512x_BCKO_SHIFT 4
|
||||
#define PCM512x_BCKP (1 << 5)
|
||||
#define PCM512x_BCKP_SHIFT 5
|
||||
|
||||
/* Page 0, Register 12 - Master mode BCK, LRCLK reset */
|
||||
#define PCM512x_RLRK (1 << 0)
|
||||
#define PCM512x_RLRK_SHIFT 0
|
||||
#define PCM512x_RBCK (1 << 1)
|
||||
#define PCM512x_RBCK_SHIFT 1
|
||||
|
||||
/* Page 0, Register 13 - PLL reference */
|
||||
#define PCM512x_SREF (1 << 4)
|
||||
#define PCM512x_SREF (7 << 4)
|
||||
#define PCM512x_SREF_SHIFT 4
|
||||
#define PCM512x_SREF_SCK (0 << 4)
|
||||
#define PCM512x_SREF_BCK (1 << 4)
|
||||
#define PCM512x_SREF_GPIO (3 << 4)
|
||||
|
||||
/* Page 0, Register 14 - DAC reference */
|
||||
#define PCM512x_SDAC (7 << 4)
|
||||
#define PCM512x_SDAC_SHIFT 4
|
||||
#define PCM512x_SDAC_MCK (0 << 4)
|
||||
#define PCM512x_SDAC_PLL (1 << 4)
|
||||
#define PCM512x_SDAC_SCK (3 << 4)
|
||||
#define PCM512x_SDAC_BCK (4 << 4)
|
||||
|
||||
/* Page 0, Register 19 - synchronize */
|
||||
#define PCM512x_RQSY (1 << 0)
|
||||
#define PCM512x_RQSY_RESUME (0 << 0)
|
||||
#define PCM512x_RQSY_HALT (1 << 0)
|
||||
|
||||
/* Page 0, Register 34 - fs speed mode */
|
||||
#define PCM512x_FSSP (3 << 0)
|
||||
#define PCM512x_FSSP_SHIFT 0
|
||||
#define PCM512x_FSSP_48KHZ (0 << 0)
|
||||
#define PCM512x_FSSP_96KHZ (1 << 0)
|
||||
#define PCM512x_FSSP_192KHZ (2 << 0)
|
||||
#define PCM512x_FSSP_384KHZ (3 << 0)
|
||||
|
||||
/* Page 0, Register 37 - Error detection */
|
||||
#define PCM512x_IPLK (1 << 0)
|
||||
@ -131,6 +172,20 @@
|
||||
#define PCM512x_IDBK (1 << 5)
|
||||
#define PCM512x_IDFS (1 << 6)
|
||||
|
||||
/* Page 0, Register 40 - I2S configuration */
|
||||
#define PCM512x_ALEN (3 << 0)
|
||||
#define PCM512x_ALEN_SHIFT 0
|
||||
#define PCM512x_ALEN_16 (0 << 0)
|
||||
#define PCM512x_ALEN_20 (1 << 0)
|
||||
#define PCM512x_ALEN_24 (2 << 0)
|
||||
#define PCM512x_ALEN_32 (3 << 0)
|
||||
#define PCM512x_AFMT (3 << 4)
|
||||
#define PCM512x_AFMT_SHIFT 4
|
||||
#define PCM512x_AFMT_I2S (0 << 4)
|
||||
#define PCM512x_AFMT_DSP (1 << 4)
|
||||
#define PCM512x_AFMT_RTJ (2 << 4)
|
||||
#define PCM512x_AFMT_LTJ (3 << 4)
|
||||
|
||||
/* Page 0, Register 42 - DAC routing */
|
||||
#define PCM512x_AUPR_SHIFT 0
|
||||
#define PCM512x_AUPL_SHIFT 4
|
||||
|
||||
Loading…
Reference in New Issue
Block a user