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[POWERPC] Merge asm-ppc/mmu_context.h into asm-power/mmu_context.h
Just did a directly merge from asm-ppc into asm-powerpc. This is the last header that we directly include from asm-powerpc. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala
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58fe255f63
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80a7cc6cf1
@ -2,16 +2,210 @@
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#define __ASM_POWERPC_MMU_CONTEXT_H
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#ifdef __KERNEL__
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#include <asm/mmu.h>
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#include <asm/cputable.h>
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#include <asm-generic/mm_hooks.h>
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#ifndef CONFIG_PPC64
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#include <asm-ppc/mmu_context.h>
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#include <asm/atomic.h>
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#include <asm/bitops.h>
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/*
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* On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
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* (virtual segment identifiers) for each context. Although the
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* hardware supports 24-bit VSIDs, and thus >1 million contexts,
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* we only use 32,768 of them. That is ample, since there can be
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* at most around 30,000 tasks in the system anyway, and it means
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* that we can use a bitmap to indicate which contexts are in use.
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* Using a bitmap means that we entirely avoid all of the problems
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* that we used to have when the context number overflowed,
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* particularly on SMP systems.
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* -- paulus.
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*/
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/*
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* This function defines the mapping from contexts to VSIDs (virtual
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* segment IDs). We use a skew on both the context and the high 4 bits
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* of the 32-bit virtual address (the "effective segment ID") in order
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* to spread out the entries in the MMU hash table. Note, if this
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* function is changed then arch/ppc/mm/hashtable.S will have to be
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* changed to correspond.
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*/
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#define CTX_TO_VSID(ctx, va) (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \
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& 0xffffff)
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/*
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The MPC8xx has only 16 contexts. We rotate through them on each
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task switch. A better way would be to keep track of tasks that
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own contexts, and implement an LRU usage. That way very active
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tasks don't always have to pay the TLB reload overhead. The
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kernel pages are mapped shared, so the kernel can run on behalf
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of any task that makes a kernel entry. Shared does not mean they
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are not protected, just that the ASID comparison is not performed.
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-- Dan
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The IBM4xx has 256 contexts, so we can just rotate through these
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as a way of "switching" contexts. If the TID of the TLB is zero,
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the PID/TID comparison is disabled, so we can use a TID of zero
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to represent all kernel pages as shared among all contexts.
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-- Dan
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*/
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static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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#ifdef CONFIG_8xx
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#define NO_CONTEXT 16
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#define LAST_CONTEXT 15
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#define FIRST_CONTEXT 0
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#elif defined(CONFIG_4xx)
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#define NO_CONTEXT 256
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#define LAST_CONTEXT 255
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#define FIRST_CONTEXT 1
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#elif defined(CONFIG_E200) || defined(CONFIG_E500)
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#define NO_CONTEXT 256
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#define LAST_CONTEXT 255
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#define FIRST_CONTEXT 1
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#else
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/* PPC 6xx, 7xx CPUs */
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#define NO_CONTEXT ((unsigned long) -1)
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#define LAST_CONTEXT 32767
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#define FIRST_CONTEXT 1
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#endif
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/*
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* Set the current MMU context.
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* On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by
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* loading up the segment registers for the user part of the address space.
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*
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* Since the PGD is immediately available, it is much faster to simply
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* pass this along as a second parameter, which is required for 8xx and
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* can be used for debugging on all processors (if you happen to have
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* an Abatron).
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*/
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extern void set_context(unsigned long contextid, pgd_t *pgd);
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/*
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* Bitmap of contexts in use.
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* The size of this bitmap is LAST_CONTEXT + 1 bits.
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*/
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extern unsigned long context_map[];
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/*
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* This caches the next context number that we expect to be free.
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* Its use is an optimization only, we can't rely on this context
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* number to be free, but it usually will be.
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*/
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extern unsigned long next_mmu_context;
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/*
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* If we don't have sufficient contexts to give one to every task
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* that could be in the system, we need to be able to steal contexts.
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* These variables support that.
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*/
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#if LAST_CONTEXT < 30000
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#define FEW_CONTEXTS 1
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extern atomic_t nr_free_contexts;
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extern struct mm_struct *context_mm[LAST_CONTEXT+1];
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extern void steal_context(void);
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#endif
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/*
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* Get a new mmu context for the address space described by `mm'.
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*/
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static inline void get_mmu_context(struct mm_struct *mm)
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{
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unsigned long ctx;
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if (mm->context.id != NO_CONTEXT)
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return;
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#ifdef FEW_CONTEXTS
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while (atomic_dec_if_positive(&nr_free_contexts) < 0)
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steal_context();
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#endif
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ctx = next_mmu_context;
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while (test_and_set_bit(ctx, context_map)) {
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ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
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if (ctx > LAST_CONTEXT)
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ctx = 0;
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}
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next_mmu_context = (ctx + 1) & LAST_CONTEXT;
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mm->context.id = ctx;
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#ifdef FEW_CONTEXTS
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context_mm[ctx] = mm;
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#endif
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}
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/*
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* Set up the context for a new address space.
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*/
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static inline int init_new_context(struct task_struct *t, struct mm_struct *mm)
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{
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mm->context.id = NO_CONTEXT;
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mm->context.vdso_base = 0;
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return 0;
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}
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/*
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* We're finished using the context for an address space.
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*/
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static inline void destroy_context(struct mm_struct *mm)
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{
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preempt_disable();
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if (mm->context.id != NO_CONTEXT) {
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clear_bit(mm->context.id, context_map);
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mm->context.id = NO_CONTEXT;
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#ifdef FEW_CONTEXTS
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atomic_inc(&nr_free_contexts);
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#endif
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}
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preempt_enable();
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}
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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#ifdef CONFIG_ALTIVEC
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if (cpu_has_feature(CPU_FTR_ALTIVEC))
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asm volatile ("dssall;\n"
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#ifndef CONFIG_POWER4
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"sync;\n" /* G4 needs a sync here, G5 apparently not */
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#endif
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: : );
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#endif /* CONFIG_ALTIVEC */
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tsk->thread.pgdir = next->pgd;
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/* No need to flush userspace segments if the mm doesnt change */
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if (prev == next)
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return;
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/* Setup new userspace context */
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get_mmu_context(next);
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set_context(next->context.id, next->pgd);
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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/*
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* After we have set current->mm to a new value, this activates
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* the context for the new mm so we see the new mappings.
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*/
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#define activate_mm(active_mm, mm) switch_mm(active_mm, mm, current)
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extern void mmu_context_init(void);
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#else
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <asm/mmu.h>
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#include <asm/cputable.h>
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#include <asm-generic/mm_hooks.h>
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/*
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* Copyright (C) 2001 PPC 64 Team, IBM Corp
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