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spi: Add RZ/V2M CSI target support
Merge series from Fabrizio Castro <fabrizio.castro.jz@renesas.com>: The CSI IP found inside the Renesas RZ/V2M SoC supports both SPI host and target. This series extends the CSI dt-bindings and driver to add SPI target support.
This commit is contained in:
Mark Brown
commit
8097dbd4b6
@ -39,6 +39,12 @@ properties:
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power-domains:
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maxItems: 1
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renesas,csi-no-ss:
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type: boolean
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description:
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The CSI Slave Selection (SS) pin won't be used to enable transmission and
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reception. Only available when in target mode.
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required:
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- compatible
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- reg
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@ -50,6 +56,9 @@ required:
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- '#address-cells'
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- '#size-cells'
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dependencies:
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renesas,csi-no-ss: [ spi-slave ]
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unevaluatedProperties: false
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examples:
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@ -862,7 +862,8 @@ config SPI_RZV2M_CSI
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tristate "Renesas RZ/V2M CSI controller"
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depends on ARCH_RENESAS || COMPILE_TEST
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help
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SPI driver for Renesas RZ/V2M Clocked Serial Interface (CSI)
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SPI driver for Renesas RZ/V2M Clocked Serial Interface (CSI).
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CSI supports both SPI host and SPI target roles.
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config SPI_QCOM_QSPI
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tristate "QTI QSPI controller"
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@ -11,6 +11,7 @@
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/log2.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/reset.h>
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@ -38,6 +39,9 @@
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#define CSI_MODE_SETUP 0x00000040
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/* CSI_CLKSEL */
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#define CSI_CLKSEL_SS_ENA BIT(19)
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#define CSI_CLKSEL_SS_POL BIT(18)
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#define CSI_CLKSEL_SS (CSI_CLKSEL_SS_ENA | CSI_CLKSEL_SS_POL)
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#define CSI_CLKSEL_CKP BIT(17)
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#define CSI_CLKSEL_DAP BIT(16)
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#define CSI_CLKSEL_MODE (CSI_CLKSEL_CKP|CSI_CLKSEL_DAP)
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@ -82,6 +86,10 @@
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#define CSI_MAX_SPI_SCKO (8 * HZ_PER_MHZ)
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#define CSI_CLKSEL_SS_DISABLED 0
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#define CSI_CLKSEL_SS_ENABLED_ACTIVE_LOW BIT(1)
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#define CSI_CLKSEL_SS_ENABLED_ACTIVE_HIGH GENMASK(1, 0)
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struct rzv2m_csi_priv {
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void __iomem *base;
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struct clk *csiclk;
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@ -99,6 +107,8 @@ struct rzv2m_csi_priv {
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wait_queue_head_t wait;
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u32 errors;
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u32 status;
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bool target_aborted;
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bool use_ss_pin;
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};
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static void rzv2m_csi_reg_write_bit(const struct rzv2m_csi_priv *csi,
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@ -193,6 +203,14 @@ static int rzv2m_csi_read_rxfifo(struct rzv2m_csi_priv *csi)
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return 0;
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}
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static inline void rzv2m_csi_empty_rxfifo(struct rzv2m_csi_priv *csi)
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{
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unsigned int i;
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for (i = 0; i < csi->words_to_transfer; i++)
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readl(csi->base + CSI_IFIFO);
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}
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static inline void rzv2m_csi_calc_current_transfer(struct rzv2m_csi_priv *csi)
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{
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unsigned int bytes_transferred = max(csi->bytes_received, csi->bytes_sent);
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@ -279,32 +297,23 @@ static int rzv2m_csi_wait_for_interrupt(struct rzv2m_csi_priv *csi,
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rzv2m_csi_enable_irqs(csi, enable_bits);
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ret = wait_event_timeout(csi->wait,
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((csi->status & wait_mask) == wait_mask) ||
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csi->errors, HZ);
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if (spi_controller_is_target(csi->controller)) {
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ret = wait_event_interruptible(csi->wait,
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((csi->status & wait_mask) == wait_mask) ||
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csi->errors || csi->target_aborted);
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if (ret || csi->target_aborted)
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ret = -EINTR;
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} else {
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ret = wait_event_timeout(csi->wait,
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((csi->status & wait_mask) == wait_mask) ||
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csi->errors, HZ) == 0 ? -ETIMEDOUT : 0;
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}
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rzv2m_csi_disable_irqs(csi, enable_bits);
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if (csi->errors)
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return -EIO;
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if (!ret)
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return -ETIMEDOUT;
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return 0;
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}
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static int rzv2m_csi_wait_for_tx_empty(struct rzv2m_csi_priv *csi)
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{
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int ret;
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if (readl(csi->base + CSI_OFIFOL) == 0)
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return 0;
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ret = rzv2m_csi_wait_for_interrupt(csi, CSI_INT_TREND, CSI_CNT_TREND_E);
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if (ret == -ETIMEDOUT)
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csi->errors |= TX_TIMEOUT_ERROR;
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return ret;
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}
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@ -312,7 +321,7 @@ static inline int rzv2m_csi_wait_for_rx_ready(struct rzv2m_csi_priv *csi)
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{
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int ret;
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if (readl(csi->base + CSI_IFIFOL) == csi->bytes_to_transfer)
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if (readl(csi->base + CSI_IFIFOL) >= csi->bytes_to_transfer)
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return 0;
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ret = rzv2m_csi_wait_for_interrupt(csi, CSI_INT_R_TRGR,
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@ -388,6 +397,7 @@ static void rzv2m_csi_setup_operating_mode(struct rzv2m_csi_priv *csi,
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static int rzv2m_csi_setup(struct spi_device *spi)
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{
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struct rzv2m_csi_priv *csi = spi_controller_get_devdata(spi->controller);
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u32 slave_selection = CSI_CLKSEL_SS_DISABLED;
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int ret;
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rzv2m_csi_sw_reset(csi, 0);
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@ -402,8 +412,17 @@ static int rzv2m_csi_setup(struct spi_device *spi)
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rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_DIR,
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!!(spi->mode & SPI_LSB_FIRST));
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/* Set the operation mode as master */
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rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_SLAVE, 0);
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/* Set the role, 1 for target and 0 for host */
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rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_SLAVE,
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!!spi_controller_is_target(csi->controller));
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if (csi->use_ss_pin)
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slave_selection = spi->mode & SPI_CS_HIGH ?
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CSI_CLKSEL_SS_ENABLED_ACTIVE_HIGH :
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CSI_CLKSEL_SS_ENABLED_ACTIVE_LOW;
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/* Configure the slave selection (SS) pin */
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rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_SS, slave_selection);
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/* Give the IP a SW reset */
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ret = rzv2m_csi_sw_reset(csi, 1);
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@ -431,9 +450,13 @@ static int rzv2m_csi_pio_transfer(struct rzv2m_csi_priv *csi)
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/* Make sure the TX FIFO is empty */
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writel(0, csi->base + CSI_OFIFOL);
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/* Make sure the RX FIFO is empty */
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writel(0, csi->base + CSI_IFIFOL);
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csi->bytes_sent = 0;
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csi->bytes_received = 0;
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csi->errors = 0;
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csi->target_aborted = false;
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rzv2m_csi_disable_all_irqs(csi);
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rzv2m_csi_clear_all_irqs(csi);
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@ -452,28 +475,21 @@ static int rzv2m_csi_pio_transfer(struct rzv2m_csi_priv *csi)
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rzv2m_csi_enable_irqs(csi, CSI_INT_OVERF | CSI_INT_UNDER);
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/* Make sure the RX FIFO is empty */
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writel(0, csi->base + CSI_IFIFOL);
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writel(readl(csi->base + CSI_INT), csi->base + CSI_INT);
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csi->status = 0;
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rzv2m_csi_start_stop_operation(csi, 1, false);
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/* TX */
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if (csi->txbuf) {
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ret = rzv2m_csi_fill_txfifo(csi);
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if (ret)
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break;
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ret = rzv2m_csi_wait_for_tx_empty(csi);
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if (ret)
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break;
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if (csi->bytes_sent == csi->buffer_len)
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tx_completed = true;
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}
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rzv2m_csi_start_stop_operation(csi, 1, false);
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/*
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* Make sure the RX FIFO contains the desired number of words.
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* We then either flush its content, or we copy it onto
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@ -483,31 +499,28 @@ static int rzv2m_csi_pio_transfer(struct rzv2m_csi_priv *csi)
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if (ret)
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break;
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/* RX */
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if (csi->rxbuf) {
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if (!spi_controller_is_target(csi->controller))
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rzv2m_csi_start_stop_operation(csi, 0, false);
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/* RX */
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if (csi->rxbuf) {
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ret = rzv2m_csi_read_rxfifo(csi);
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if (ret)
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break;
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if (csi->bytes_received == csi->buffer_len)
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rx_completed = true;
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} else {
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rzv2m_csi_empty_rxfifo(csi);
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}
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ret = rzv2m_csi_start_stop_operation(csi, 0, true);
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if (ret)
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goto pio_quit;
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if (csi->errors) {
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ret = -EIO;
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goto pio_quit;
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break;
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}
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}
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rzv2m_csi_start_stop_operation(csi, 0, true);
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pio_quit:
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rzv2m_csi_disable_all_irqs(csi);
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rzv2m_csi_enable_rx_trigger(csi, false);
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rzv2m_csi_clear_all_irqs(csi);
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@ -529,7 +542,8 @@ static int rzv2m_csi_transfer_one(struct spi_controller *controller,
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rzv2m_csi_setup_operating_mode(csi, transfer);
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rzv2m_csi_setup_clock(csi, transfer->speed_hz);
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if (!spi_controller_is_target(csi->controller))
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rzv2m_csi_setup_clock(csi, transfer->speed_hz);
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ret = rzv2m_csi_pio_transfer(csi);
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if (ret) {
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@ -546,24 +560,48 @@ static int rzv2m_csi_transfer_one(struct spi_controller *controller,
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return ret;
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}
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static int rzv2m_csi_target_abort(struct spi_controller *ctlr)
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{
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struct rzv2m_csi_priv *csi = spi_controller_get_devdata(ctlr);
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csi->target_aborted = true;
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wake_up(&csi->wait);
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return 0;
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}
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static int rzv2m_csi_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct spi_controller *controller;
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struct device *dev = &pdev->dev;
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struct rzv2m_csi_priv *csi;
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struct reset_control *rstc;
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bool target_mode;
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int irq;
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int ret;
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controller = devm_spi_alloc_host(dev, sizeof(*csi));
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target_mode = of_property_read_bool(np, "spi-slave");
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if (target_mode)
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controller = devm_spi_alloc_target(dev, sizeof(*csi));
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else
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controller = devm_spi_alloc_host(dev, sizeof(*csi));
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if (!controller)
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return -ENOMEM;
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csi = spi_controller_get_devdata(controller);
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platform_set_drvdata(pdev, csi);
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csi->use_ss_pin = false;
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if (spi_controller_is_target(controller) &&
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!of_property_read_bool(np, "renesas,csi-no-ss"))
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csi->use_ss_pin = true;
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csi->dev = dev;
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csi->controller = controller;
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csi->target_aborted = false;
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csi->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(csi->base))
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@ -589,11 +627,12 @@ static int rzv2m_csi_probe(struct platform_device *pdev)
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init_waitqueue_head(&csi->wait);
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controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
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controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH;
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controller->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
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controller->setup = rzv2m_csi_setup;
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controller->transfer_one = rzv2m_csi_transfer_one;
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controller->use_gpio_descriptors = true;
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controller->target_abort = rzv2m_csi_target_abort;
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device_set_node(&controller->dev, dev_fwnode(dev));
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