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ath9k: Enable extended synch for AR9485 to fix L0s recovery issue
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -131,6 +131,7 @@ struct ath_bus_ops {
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void (*read_cachesize)(struct ath_common *common, int *csz);
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bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
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void (*bt_coex_prep)(struct ath_common *common);
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void (*extn_synch_en)(struct ath_common *common);
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};
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struct ath_common {
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@ -1971,6 +1971,11 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
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if (AR_SREV_9485_10(ah)) {
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pCap->pcie_lcr_extsync_en = true;
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pCap->pcie_lcr_offset = 0x80;
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}
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return 0;
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}
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@ -209,6 +209,8 @@ struct ath9k_hw_capabilities {
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u8 rx_status_len;
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u8 tx_desc_len;
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u8 txs_len;
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u16 pcie_lcr_offset;
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bool pcie_lcr_extsync_en;
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};
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struct ath9k_ops_config {
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@ -1179,6 +1179,9 @@ static int ath9k_start(struct ieee80211_hw *hw)
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pm_qos_update_request(&sc->pm_qos_req, 55);
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if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
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common->bus_ops->extn_synch_en(common);
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mutex_unlock:
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mutex_unlock(&sc->mutex);
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@ -103,11 +103,23 @@ static void ath_pci_bt_coex_prep(struct ath_common *common)
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pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
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}
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static void ath_pci_extn_synch_enable(struct ath_common *common)
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{
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struct ath_softc *sc = (struct ath_softc *) common->priv;
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struct pci_dev *pdev = to_pci_dev(sc->dev);
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u8 lnkctl;
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pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
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lnkctl |= PCI_EXP_LNKCTL_ES;
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pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
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}
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static const struct ath_bus_ops ath_pci_bus_ops = {
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.ath_bus_type = ATH_PCI,
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.read_cachesize = ath_pci_read_cachesize,
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.eeprom_read = ath_pci_eeprom_read,
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.bt_coex_prep = ath_pci_bt_coex_prep,
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.extn_synch_en = ath_pci_extn_synch_enable,
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};
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static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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