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staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function
Function 'mt7621_pcie_enable_ports' tries to enable all PCI ports. To make it more readable the single port initialization part has been factor out into a new 'mt7621_pcie_enable_port' function. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1e80699fd6
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@ -628,54 +628,64 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
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}
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}
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static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
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{
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struct mt7621_pcie *pcie = port->pcie;
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u32 slot = port->slot;
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u32 offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
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u32 val;
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int err;
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/* assert port PERST_N */
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val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
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val |= PCIE_PORT_PERST(slot);
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pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
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/* de-assert port PERST_N */
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val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
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val &= ~PCIE_PORT_PERST(slot);
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pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
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/* 100ms timeout value should be enough for Gen1 training */
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err = readl_poll_timeout(port->base + RALINK_PCI_STATUS,
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val, !!(val & PCIE_PORT_LINKUP),
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20, 100 * USEC_PER_MSEC);
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if (err)
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return -ETIMEDOUT;
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/* enable pcie interrupt */
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val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
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val |= PCIE_PORT_INT_EN(slot);
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pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
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/* map 2G DDR region */
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pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
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offset + RALINK_PCI_BAR0SETUP_ADDR);
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pcie_write(pcie, MEMORY_BASE,
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offset + RALINK_PCI_IMBASEBAR0_ADDR);
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/* configure class code and revision ID */
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pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
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offset + RALINK_PCI_CLASS);
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return 0;
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}
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static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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struct mt7621_pcie_port *port;
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u8 num_slots_enabled = 0;
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u32 offset;
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u32 slot;
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u32 val;
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int err;
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list_for_each_entry(port, &pcie->ports, list) {
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slot = port->slot;
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offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
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if (port->enabled) {
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/* assert port PERST_N */
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val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
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val |= PCIE_PORT_PERST(slot);
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pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
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/* de-assert port PERST_N */
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val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
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val &= ~PCIE_PORT_PERST(slot);
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pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
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/* 100ms timeout value should be enough for Gen1 training */
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err = readl_poll_timeout(port->base + RALINK_PCI_STATUS,
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val,!!(val & PCIE_PORT_LINKUP),
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20, 100 * USEC_PER_MSEC);
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if (err) {
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if (!mt7621_pcie_enable_port(port)) {
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dev_err(dev, "de-assert port %d PERST_N\n",
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slot);
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port->slot);
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continue;
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}
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/* enable pcie interrupt */
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val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
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val |= PCIE_PORT_INT_EN(slot);
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pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
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/* map 2G DDR region */
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pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
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offset + RALINK_PCI_BAR0SETUP_ADDR);
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pcie_write(pcie, MEMORY_BASE,
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offset + RALINK_PCI_IMBASEBAR0_ADDR);
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/* configure class code and revision ID */
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pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
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offset + RALINK_PCI_CLASS);
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dev_info(dev, "PCIE%d enabled\n", slot);
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num_slots_enabled++;
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}
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