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sh: TLB fast path optimizations for load/store exceptions.
This only bothers with the TLB entry flush in the case of the initial page write exception, as it is unecessary in the case of the load/store exceptions. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -124,7 +124,7 @@ ENTRY(tlb_miss_store)
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.align 2
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ENTRY(initial_page_write)
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bra call_handle_tlbmiss
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mov #1, r5
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mov #2, r5
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.align 2
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ENTRY(tlb_protection_violation_load)
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@ -327,7 +327,6 @@ handle_tlbmiss(struct pt_regs *regs, unsigned long writeaccess,
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pmd_t *pmd;
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pte_t *pte;
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pte_t entry;
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int ret = 1;
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/*
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* We don't take page faults for P1, P2, and parts of P4, these
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@ -338,40 +337,41 @@ handle_tlbmiss(struct pt_regs *regs, unsigned long writeaccess,
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pgd = pgd_offset_k(address);
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} else {
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if (unlikely(address >= TASK_SIZE || !current->mm))
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goto out;
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return 1;
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pgd = pgd_offset(current->mm, address);
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}
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pud = pud_offset(pgd, address);
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if (pud_none_or_clear_bad(pud))
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goto out;
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return 1;
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pmd = pmd_offset(pud, address);
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if (pmd_none_or_clear_bad(pmd))
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goto out;
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return 1;
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pte = pte_offset_kernel(pmd, address);
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entry = *pte;
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if (unlikely(pte_none(entry) || pte_not_present(entry)))
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goto out;
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return 1;
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if (unlikely(writeaccess && !pte_write(entry)))
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goto out;
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return 1;
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if (writeaccess)
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entry = pte_mkdirty(entry);
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entry = pte_mkyoung(entry);
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set_pte(pte, entry);
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#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SMP)
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/*
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* ITLB is not affected by "ldtlb" instruction.
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* So, we need to flush the entry by ourselves.
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* SH-4 does not set MMUCR.RC to the corresponding TLB entry in
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* the case of an initial page write exception, so we need to
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* flush it in order to avoid potential TLB entry duplication.
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*/
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local_flush_tlb_one(get_asid(), address & PAGE_MASK);
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if (writeaccess == 2)
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local_flush_tlb_one(get_asid(), address & PAGE_MASK);
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#endif
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set_pte(pte, entry);
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update_mmu_cache(NULL, address, entry);
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ret = 0;
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out:
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return ret;
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return 0;
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}
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