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https://github.com/torvalds/linux.git
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Merge branch 'remotes/lorenzo/pci/aardvark'
- Add bridge emulation definitions for PCIe DEVCAP2, DEVCTL2, DEVSTA2, LNKCAP2, LNKCTL2, LNKSTA2, SLTCAP2, SLTCTL2, SLTSTA2 (Pali Rohár) - Add aardvark support for DEVCAP2, DEVCTL2, LNKCAP2 and LNKCTL2 registers (Pali Rohár) - Clear all MSIs at setup to avoid spurious interrupts (Pali Rohár) - Disable bus mastering when unbinding host controller driver (Pali Rohár) - Mask all interrupts when unbinding host controller driver (Pali Rohár) - Fix memory leak in host controller unbind (Pali Rohár) - Assert PERST# when unbinding host controller driver (Pali Rohár) - Disable link training when unbinding host controller driver (Pali Rohár) - Disable common PHY when unbinding host controller driver (Pali Rohár) - Fix resource type checking to check only IORESOURCE_MEM, not IORESOURCE_MEM_64, which is a flavor of IORESOURCE_MEM (Pali Rohár) * remotes/lorenzo/pci/aardvark: PCI: aardvark: Fix checking for MEM resource type PCI: aardvark: Disable common PHY when unbinding driver PCI: aardvark: Disable link training when unbinding driver PCI: aardvark: Assert PERST# when unbinding driver PCI: aardvark: Fix memory leak in driver unbind PCI: aardvark: Mask all interrupts when unbinding driver PCI: aardvark: Disable bus mastering when unbinding driver PCI: aardvark: Comment actions in driver remove method PCI: aardvark: Clear all MSIs at setup PCI: aardvark: Add support for DEVCAP2, DEVCTL2, LNKCAP2 and LNKCTL2 registers on emulated bridge PCI: pci-bridge-emul: Add definitions for missing capabilities registers PCI: pci-bridge-emul: Add description for class_revision field
This commit is contained in:
Bjorn Helgaas
commit
800cee8b04
@ -116,6 +116,7 @@
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#define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
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#define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
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#define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
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#define PCIE_MSI_ALL_MASK GENMASK(31, 0)
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#define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
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#define PCIE_MSI_DATA_MASK GENMASK(15, 0)
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@ -571,6 +572,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
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/* Clear all interrupts */
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advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
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advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
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advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
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advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
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@ -583,7 +585,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
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/* Unmask all MSIs */
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advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
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advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
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/* Enable summary interrupt for GIC SPI source */
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reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
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@ -884,8 +886,13 @@ advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
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case PCI_CAP_LIST_ID:
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case PCI_EXP_DEVCAP:
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case PCI_EXP_DEVCTL:
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case PCI_EXP_DEVCAP2:
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case PCI_EXP_DEVCTL2:
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case PCI_EXP_LNKCAP2:
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case PCI_EXP_LNKCTL2:
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*value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
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return PCI_BRIDGE_EMUL_HANDLED;
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default:
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return PCI_BRIDGE_EMUL_NOT_HANDLED;
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}
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@ -899,10 +906,6 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
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struct advk_pcie *pcie = bridge->data;
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switch (reg) {
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case PCI_EXP_DEVCTL:
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advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
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break;
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case PCI_EXP_LNKCTL:
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advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
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if (new & PCI_EXP_LNKCTL_RL)
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@ -924,6 +927,12 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
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advk_writel(pcie, new, PCIE_ISR0_REG);
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break;
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case PCI_EXP_DEVCTL:
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case PCI_EXP_DEVCTL2:
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case PCI_EXP_LNKCTL2:
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advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
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break;
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default:
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break;
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}
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@ -1392,7 +1401,7 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
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msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
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msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
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msi_status = msi_val & ~msi_mask;
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msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK);
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for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
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if (!(BIT(msi_idx) & msi_status))
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@ -1544,8 +1553,7 @@ static int advk_pcie_probe(struct platform_device *pdev)
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* only PIO for issuing configuration transfers which does
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* not use PCIe window configuration.
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*/
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if (type != IORESOURCE_MEM && type != IORESOURCE_MEM_64 &&
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type != IORESOURCE_IO)
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if (type != IORESOURCE_MEM && type != IORESOURCE_IO)
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continue;
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/*
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@ -1553,8 +1561,7 @@ static int advk_pcie_probe(struct platform_device *pdev)
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* configuration is set to transparent memory access so it
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* does not need window configuration.
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*/
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if ((type == IORESOURCE_MEM || type == IORESOURCE_MEM_64) &&
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entry->offset == 0)
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if (type == IORESOURCE_MEM && entry->offset == 0)
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continue;
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/*
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@ -1686,20 +1693,64 @@ static int advk_pcie_remove(struct platform_device *pdev)
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{
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struct advk_pcie *pcie = platform_get_drvdata(pdev);
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struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
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u32 val;
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int i;
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/* Remove PCI bus with all devices */
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pci_lock_rescan_remove();
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pci_stop_root_bus(bridge->bus);
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pci_remove_root_bus(bridge->bus);
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pci_unlock_rescan_remove();
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/* Disable Root Bridge I/O space, memory space and bus mastering */
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val = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
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val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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advk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG);
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/* Disable MSI */
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val = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
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val &= ~PCIE_CORE_CTRL2_MSI_ENABLE;
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advk_writel(pcie, val, PCIE_CORE_CTRL2_REG);
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/* Clear MSI address */
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advk_writel(pcie, 0, PCIE_MSI_ADDR_LOW_REG);
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advk_writel(pcie, 0, PCIE_MSI_ADDR_HIGH_REG);
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/* Mask all interrupts */
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advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
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advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);
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advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
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advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_MASK_REG);
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/* Clear all interrupts */
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advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
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advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
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advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
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advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
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/* Remove IRQ domains */
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advk_pcie_remove_msi_irq_domain(pcie);
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advk_pcie_remove_irq_domain(pcie);
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/* Free config space for emulated root bridge */
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pci_bridge_emul_cleanup(&pcie->bridge);
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/* Assert PERST# signal which prepares PCIe card for power down */
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if (pcie->reset_gpio)
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gpiod_set_value_cansleep(pcie->reset_gpio, 1);
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/* Disable link training */
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val = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
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val &= ~LINK_TRAINING_EN;
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advk_writel(pcie, val, PCIE_CORE_CTRL0_REG);
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/* Disable outbound address windows mapping */
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for (i = 0; i < OB_WIN_COUNT; i++)
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advk_pcie_disable_ob_win(pcie, i);
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/* Disable phy */
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advk_pcie_disable_phy(pcie);
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return 0;
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}
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@ -251,6 +251,49 @@ struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] =
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.ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
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.w1c = PCI_EXP_RTSTA_PME,
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},
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[PCI_EXP_DEVCAP2 / 4] = {
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/*
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* Device capabilities 2 register has reserved bits [30:27].
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* Also bits [26:24] are reserved for non-upstream ports.
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*/
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.ro = BIT(31) | GENMASK(23, 0),
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},
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[PCI_EXP_DEVCTL2 / 4] = {
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/*
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* Device control 2 register is RW. Bit 11 is reserved for
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* non-upstream ports.
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*
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* Device status 2 register is reserved.
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*/
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.rw = GENMASK(15, 12) | GENMASK(10, 0),
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},
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[PCI_EXP_LNKCAP2 / 4] = {
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/* Link capabilities 2 register has reserved bits [30:25] and 0. */
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.ro = BIT(31) | GENMASK(24, 1),
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},
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[PCI_EXP_LNKCTL2 / 4] = {
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/*
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* Link control 2 register is RW.
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*
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* Link status 2 register has bits 5, 15 W1C;
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* bits 10, 11 reserved and others are RO.
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*/
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.rw = GENMASK(15, 0),
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.w1c = (BIT(15) | BIT(5)) << 16,
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.ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,
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},
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[PCI_EXP_SLTCAP2 / 4] = {
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/* Slot capabilities 2 register is reserved. */
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},
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[PCI_EXP_SLTCTL2 / 4] = {
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/* Both Slot control 2 and Slot status 2 registers are reserved. */
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},
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};
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/*
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@ -265,7 +308,11 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
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{
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BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);
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bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);
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/*
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* class_revision: Class is high 24 bits and revision is low 8 bit of this member,
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* while class for PCI Bridge Normal Decode has the 24-bit value: PCI_CLASS_BRIDGE_PCI << 8
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*/
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bridge->conf.class_revision |= cpu_to_le32((PCI_CLASS_BRIDGE_PCI << 8) << 8);
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bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
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bridge->conf.cache_line_size = 0x10;
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bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
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