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rdma/cxgb4: Add support for srq functions & structs
This patch adds kernel mode t4_srq structures and support functions, uapi structures and defines, as well as firmware work request structures. Signed-off-by: Raju Rangoju <rajur@chelsio.com> Reviewed-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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@ -97,6 +97,7 @@ struct c4iw_resource {
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struct c4iw_id_table tpt_table;
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struct c4iw_id_table qid_table;
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struct c4iw_id_table pdid_table;
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struct c4iw_id_table srq_table;
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};
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struct c4iw_qid_list {
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@ -130,6 +131,8 @@ struct c4iw_stats {
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struct c4iw_stat stag;
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struct c4iw_stat pbl;
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struct c4iw_stat rqt;
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struct c4iw_stat srqt;
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struct c4iw_stat srq;
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struct c4iw_stat ocqp;
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u64 db_full;
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u64 db_empty;
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@ -549,6 +552,7 @@ struct c4iw_qp {
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struct kref kref;
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wait_queue_head_t wait;
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int sq_sig_all;
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struct c4iw_srq *srq;
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struct work_struct free_work;
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struct c4iw_ucontext *ucontext;
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struct c4iw_wr_wait *wr_waitp;
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@ -559,6 +563,26 @@ static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
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return container_of(ibqp, struct c4iw_qp, ibqp);
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}
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struct c4iw_srq {
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struct ib_srq ibsrq;
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struct list_head db_fc_entry;
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struct c4iw_dev *rhp;
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struct t4_srq wq;
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struct sk_buff *destroy_skb;
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u32 srq_limit;
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u32 pdid;
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int idx;
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u32 flags;
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spinlock_t lock; /* protects srq */
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struct c4iw_wr_wait *wr_waitp;
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bool armed;
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};
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static inline struct c4iw_srq *to_c4iw_srq(struct ib_srq *ibsrq)
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{
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return container_of(ibsrq, struct c4iw_srq, ibsrq);
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}
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struct c4iw_ucontext {
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struct ib_ucontext ibucontext;
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struct c4iw_dev_ucontext uctx;
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@ -1040,6 +1064,13 @@ struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
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struct ib_udata *udata);
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int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
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int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
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int c4iw_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *attr,
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enum ib_srq_attr_mask srq_attr_mask,
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struct ib_udata *udata);
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int c4iw_destroy_srq(struct ib_srq *ib_srq);
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struct ib_srq *c4iw_create_srq(struct ib_pd *pd,
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struct ib_srq_init_attr *attrs,
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struct ib_udata *udata);
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int c4iw_destroy_qp(struct ib_qp *ib_qp);
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struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
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struct ib_qp_init_attr *attrs,
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@ -1076,12 +1107,19 @@ extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
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void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
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enum cxgb4_bar2_qtype qtype,
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unsigned int *pbar2_qid, u64 *pbar2_pa);
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int c4iw_alloc_srq_idx(struct c4iw_rdev *rdev);
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void c4iw_free_srq_idx(struct c4iw_rdev *rdev, int idx);
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extern void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe);
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extern int c4iw_wr_log;
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extern int db_fc_threshold;
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extern int db_coalescing_threshold;
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extern int use_dsgl;
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void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey);
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void c4iw_dispatch_srq_limit_reached_event(struct c4iw_srq *srq);
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void c4iw_copy_wr_to_srq(struct t4_srq *srq, union t4_recv_wr *wqe, u8 len16);
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void c4iw_flush_srqidx(struct c4iw_qp *qhp, u32 srqidx);
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int c4iw_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
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struct ib_recv_wr **bad_wr);
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struct c4iw_wr_wait *c4iw_alloc_wr_wait(gfp_t gfp);
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typedef int c4iw_restrack_func(struct sk_buff *msg,
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@ -52,12 +52,16 @@ struct t4_status_page {
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__be16 pidx;
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u8 qp_err; /* flit 1 - sw owns */
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u8 db_off;
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u8 pad;
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u8 pad[2];
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u16 host_wq_pidx;
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u16 host_cidx;
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u16 host_pidx;
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u16 pad2;
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u32 srqidx;
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};
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#define T4_RQT_ENTRY_SHIFT 6
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#define T4_RQT_ENTRY_SIZE BIT(T4_RQT_ENTRY_SHIFT)
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#define T4_EQ_ENTRY_SIZE 64
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#define T4_SQ_NUM_SLOTS 5
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@ -248,6 +252,7 @@ struct t4_cqe {
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/* used for RQ completion processing */
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#define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
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#define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
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#define CQE_ABS_RQE_IDX(x) (be32_to_cpu((x)->u.srcqe.abs_rqe_idx))
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/* used for SQ completion processing */
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#define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
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@ -331,6 +336,7 @@ struct t4_swrqe {
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u64 wr_id;
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ktime_t host_time;
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u64 sge_ts;
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int valid;
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};
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struct t4_rq {
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@ -360,8 +366,98 @@ struct t4_wq {
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void __iomem *db;
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struct c4iw_rdev *rdev;
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int flushed;
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u8 *qp_errp;
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u32 *srqidxp;
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};
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struct t4_srq_pending_wr {
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u64 wr_id;
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union t4_recv_wr wqe;
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u8 len16;
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};
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struct t4_srq {
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union t4_recv_wr *queue;
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dma_addr_t dma_addr;
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DECLARE_PCI_UNMAP_ADDR(mapping);
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struct t4_swrqe *sw_rq;
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void __iomem *bar2_va;
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u64 bar2_pa;
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size_t memsize;
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u32 bar2_qid;
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u32 qid;
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u32 msn;
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u32 rqt_hwaddr;
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u32 rqt_abs_idx;
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u16 rqt_size;
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u16 size;
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u16 cidx;
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u16 pidx;
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u16 wq_pidx;
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u16 wq_pidx_inc;
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u16 in_use;
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struct t4_srq_pending_wr *pending_wrs;
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u16 pending_cidx;
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u16 pending_pidx;
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u16 pending_in_use;
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u16 ooo_count;
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};
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static inline u32 t4_srq_avail(struct t4_srq *srq)
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{
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return srq->size - 1 - srq->in_use;
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}
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static inline void t4_srq_produce(struct t4_srq *srq, u8 len16)
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{
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srq->in_use++;
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if (++srq->pidx == srq->size)
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srq->pidx = 0;
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srq->wq_pidx += DIV_ROUND_UP(len16 * 16, T4_EQ_ENTRY_SIZE);
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if (srq->wq_pidx >= srq->size * T4_RQ_NUM_SLOTS)
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srq->wq_pidx %= srq->size * T4_RQ_NUM_SLOTS;
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srq->queue[srq->size].status.host_pidx = srq->pidx;
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}
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static inline void t4_srq_produce_pending_wr(struct t4_srq *srq)
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{
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srq->pending_in_use++;
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srq->in_use++;
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if (++srq->pending_pidx == srq->size)
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srq->pending_pidx = 0;
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}
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static inline void t4_srq_consume_pending_wr(struct t4_srq *srq)
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{
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srq->pending_in_use--;
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srq->in_use--;
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if (++srq->pending_cidx == srq->size)
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srq->pending_cidx = 0;
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}
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static inline void t4_srq_produce_ooo(struct t4_srq *srq)
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{
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srq->in_use--;
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srq->ooo_count++;
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}
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static inline void t4_srq_consume_ooo(struct t4_srq *srq)
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{
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srq->cidx++;
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if (srq->cidx == srq->size)
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srq->cidx = 0;
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srq->queue[srq->size].status.host_cidx = srq->cidx;
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srq->ooo_count--;
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}
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static inline void t4_srq_consume(struct t4_srq *srq)
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{
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srq->in_use--;
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if (++srq->cidx == srq->size)
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srq->cidx = 0;
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srq->queue[srq->size].status.host_cidx = srq->cidx;
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}
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static inline int t4_rqes_posted(struct t4_wq *wq)
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{
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return wq->rq.in_use;
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@ -475,6 +571,25 @@ static inline void pio_copy(u64 __iomem *dst, u64 *src)
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}
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}
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static inline void t4_ring_srq_db(struct t4_srq *srq, u16 inc, u8 len16,
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union t4_recv_wr *wqe)
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{
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/* Flush host queue memory writes. */
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wmb();
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if (inc == 1 && srq->bar2_qid == 0 && wqe) {
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pr_debug("%s : WC srq->pidx = %d; len16=%d\n",
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__func__, srq->pidx, len16);
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pio_copy(srq->bar2_va + SGE_UDB_WCDOORBELL, (u64 *)wqe);
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} else {
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pr_debug("%s: DB srq->pidx = %d; len16=%d\n",
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__func__, srq->pidx, len16);
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writel(PIDX_T5_V(inc) | QID_V(srq->bar2_qid),
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srq->bar2_va + SGE_UDB_KDOORBELL);
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}
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/* Flush user doorbell area writes. */
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wmb();
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}
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static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, union t4_wr *wqe)
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{
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@ -263,6 +263,7 @@ enum fw_ri_res_type {
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FW_RI_RES_TYPE_SQ,
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FW_RI_RES_TYPE_RQ,
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FW_RI_RES_TYPE_CQ,
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FW_RI_RES_TYPE_SRQ,
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};
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enum fw_ri_res_op {
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@ -296,6 +297,20 @@ struct fw_ri_res {
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__be32 r6_lo;
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__be64 r7;
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} cq;
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struct fw_ri_res_srq {
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__u8 restype;
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__u8 op;
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__be16 r3;
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__be32 eqid;
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__be32 r4[2];
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__be32 fetchszm_to_iqid;
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__be32 dcaen_to_eqsize;
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__be64 eqaddr;
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__be32 srqid;
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__be32 pdid;
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__be32 hwsrqsize;
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__be32 hwsrqaddr;
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} srq;
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} u;
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};
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@ -707,6 +722,10 @@ enum fw_ri_init_p2ptype {
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FW_RI_INIT_P2PTYPE_DISABLED = 0xf,
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};
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enum fw_ri_init_rqeqid_srq {
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FW_RI_INIT_RQEQID_SRQ = 1 << 31,
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};
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struct fw_ri_wr {
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__be32 op_compl;
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__be32 flowid_len16;
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@ -84,6 +84,23 @@ struct c4iw_create_qp_resp {
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__u32 flags;
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};
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struct c4iw_create_srq_resp {
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__aligned_u64 srq_key;
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__aligned_u64 srq_db_gts_key;
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__aligned_u64 srq_memsize;
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__u32 srqid;
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__u32 srq_size;
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__u32 rqt_abs_idx;
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__u32 qid_mask;
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__u32 flags;
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__u32 reserved; /* explicit padding */
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};
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enum {
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/* HW supports SRQ_LIMIT_REACHED event */
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T4_SRQ_LIMIT_SUPPORT = 1 << 0,
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};
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struct c4iw_alloc_ucontext_resp {
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__aligned_u64 status_page_key;
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__u32 status_page_size;
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