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[ARM] 4341/1: iop13xx: fix i/o address translation
PCI devices were being programmed with an incorrect base address value. This patch moves I/O space into a 16-bit addressable region and corrects the i/o offset. Much thanks to Martin Michlmayr for tracking this issue and testing debug patches. Cc: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -1023,7 +1023,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
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<< IOP13XX_ATUX_PCIXSR_FUNC_NUM;
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__raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
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res[0].start = IOP13XX_PCIX_LOWER_IO_PA;
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res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET;
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res[0].end = IOP13XX_PCIX_UPPER_IO_PA;
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res[0].name = "IQ81340 ATUX PCI I/O Space";
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res[0].flags = IORESOURCE_IO;
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@ -1033,7 +1033,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
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res[1].name = "IQ81340 ATUX PCI Memory Space";
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res[1].flags = IORESOURCE_MEM;
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sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
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sys->io_offset = IOP13XX_PCIX_IO_OFFSET;
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sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA;
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break;
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case IOP13XX_INIT_ATU_ATUE:
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/* Note: the function number field in the PCSR is ro */
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@ -1044,7 +1044,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
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__raw_writel(pcsr, IOP13XX_ATUE_PCSR);
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res[0].start = IOP13XX_PCIE_LOWER_IO_PA;
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res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET;
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res[0].end = IOP13XX_PCIE_UPPER_IO_PA;
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res[0].name = "IQ81340 ATUE PCI I/O Space";
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res[0].flags = IORESOURCE_IO;
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@ -1054,7 +1054,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
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res[1].name = "IQ81340 ATUE PCI Memory Space";
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res[1].flags = IORESOURCE_MEM;
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sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
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sys->io_offset = IOP13XX_PCIE_IO_OFFSET;
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sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA;
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sys->map_irq = iop13xx_pcie_map_irq;
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break;
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default:
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@ -27,19 +27,24 @@ static inline int iop13xx_cpu_id(void)
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#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
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/* PCI MAP
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* 0x0000.0000 - 0x8000.0000 1:1 mapping with Physical RAM
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* 0x8000.0000 - 0x8800.0000 PCIX/PCIE memory window (128MB)
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*/
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* bus range cpu phys cpu virt note
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* 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM
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* 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window
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* 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
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*
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* IO MAP
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* 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window
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* 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window
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*/
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#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
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#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
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#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
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#define IOP13XX_PCIX_LOWER_IO_BA 0x0fff0000UL
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#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
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#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL
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#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
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IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
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#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
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IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
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#define IOP13XX_PCIX_IO_OFFSET (IOP13XX_PCIX_LOWER_IO_VA -\
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IOP13XX_PCIX_LOWER_IO_BA)
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#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
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(IOP13XX_PCIX_LOWER_IO_PA\
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- IOP13XX_PCIX_LOWER_IO_VA))
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@ -65,15 +70,14 @@ static inline int iop13xx_cpu_id(void)
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#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
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#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
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#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL
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#define IOP13XX_PCIE_LOWER_IO_BA 0x0fff0000UL
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#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */
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#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL
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#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
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IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
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#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
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IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
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#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
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IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
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#define IOP13XX_PCIE_IO_OFFSET (IOP13XX_PCIE_LOWER_IO_VA -\
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IOP13XX_PCIE_LOWER_IO_BA)
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#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
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(IOP13XX_PCIE_LOWER_IO_PA\
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- IOP13XX_PCIE_LOWER_IO_VA))
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