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Add SOF support for ACP7.0 based platform
Merge series from Vijendar Mukunda <Vijendar.Mukunda@amd.com>: This patch series adds SOF support for ACP7.0 based platform. Link: https://github.com/thesofproject/linux/pull/5139
This commit is contained in:
Mark Brown
commit
7db4491488
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@ -321,5 +321,17 @@ struct snd_soc_acpi_mach snd_soc_acpi_amd_acp63_sof_machines[] = {
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};
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EXPORT_SYMBOL(snd_soc_acpi_amd_acp63_sof_machines);
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struct snd_soc_acpi_mach snd_soc_acpi_amd_acp70_sof_machines[] = {
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{
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.id = "AMDI1010",
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.drv_name = "acp70-dsp",
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.pdata = &acp_quirk_data,
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.fw_filename = "sof-acp_7_0.ri",
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.sof_tplg_filename = "sof-acp_7_0.tplg",
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},
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{},
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};
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EXPORT_SYMBOL(snd_soc_acpi_amd_acp70_sof_machines);
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MODULE_DESCRIPTION("AMD ACP Machine Configuration Module");
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MODULE_LICENSE("Dual BSD/GPL");
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@ -24,6 +24,7 @@ extern struct snd_soc_acpi_mach snd_soc_acpi_amd_rmb_sof_machines[];
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extern struct snd_soc_acpi_mach snd_soc_acpi_amd_vangogh_sof_machines[];
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extern struct snd_soc_acpi_mach snd_soc_acpi_amd_acp63_sof_machines[];
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extern struct snd_soc_acpi_mach snd_soc_acpi_amd_acp63_sof_sdw_machines[];
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extern struct snd_soc_acpi_mach snd_soc_acpi_amd_acp70_sof_machines[];
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struct config_entry {
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u32 flags;
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@ -88,4 +88,14 @@ config SND_SOC_SOF_AMD_ACP63
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AMD ACP6.3 version based platforms.
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Say Y if you want to enable SOF on ACP6.3 based platform.
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If unsure select "N".
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config SND_SOC_SOF_AMD_ACP70
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tristate "SOF support for ACP7.0 platform"
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depends on SND_SOC_SOF_PCI
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select SND_SOC_SOF_AMD_COMMON
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help
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Select this option for SOF support on
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AMD ACP7.0 version based platforms.
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Say Y if you want to enable SOF on ACP7.0 based platform.
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endif
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@ -2,7 +2,7 @@
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# This file is provided under a dual BSD/GPLv2 license. When using or
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# redistributing this file, you may do so under either license.
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#
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# Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
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# Copyright(c) 2021, 2023, 2024 Advanced Micro Devices, Inc. All rights reserved.
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snd-sof-amd-acp-y := acp.o acp-loader.o acp-ipc.o acp-pcm.o acp-stream.o acp-trace.o acp-common.o
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snd-sof-amd-acp-$(CONFIG_SND_SOC_SOF_ACP_PROBES) += acp-probes.o
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@ -10,9 +10,11 @@ snd-sof-amd-renoir-y := pci-rn.o renoir.o
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snd-sof-amd-rembrandt-y := pci-rmb.o rembrandt.o
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snd-sof-amd-vangogh-y := pci-vangogh.o vangogh.o
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snd-sof-amd-acp63-y := pci-acp63.o acp63.o
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snd-sof-amd-acp70-y := pci-acp70.o acp70.o
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obj-$(CONFIG_SND_SOC_SOF_AMD_COMMON) += snd-sof-amd-acp.o
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obj-$(CONFIG_SND_SOC_SOF_AMD_RENOIR) += snd-sof-amd-renoir.o
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obj-$(CONFIG_SND_SOC_SOF_AMD_REMBRANDT) += snd-sof-amd-rembrandt.o
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obj-$(CONFIG_SND_SOC_SOF_AMD_VANGOGH) += snd-sof-amd-vangogh.o
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obj-$(CONFIG_SND_SOC_SOF_AMD_ACP63) += snd-sof-amd-acp63.o
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obj-$(CONFIG_SND_SOC_SOF_AMD_ACP70) += snd-sof-amd-acp70.o
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@ -3,7 +3,7 @@
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
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* Copyright(c) 2021, 2023, 2024 Advanced Micro Devices, Inc. All rights reserved.
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*
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* Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
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*/
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@ -23,6 +23,17 @@
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#define ACP_DMA_CH_STS 0xE8
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#define ACP_DMA_CH_GROUP 0xEC
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#define ACP_DMA_CH_RST_STS 0xF0
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#define ACP70_DMA_CNTL_0 0x00
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#define ACP70_DMA_DSCR_STRT_IDX_0 0x28
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#define ACP70_DMA_DSCR_CNT_0 0x50
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#define ACP70_DMA_PRIO_0 0x78
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#define ACP70_DMA_CUR_DSCR_0 0xA0
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#define ACP70_DMA_ERR_STS_0 0xF0
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#define ACP70_DMA_DESC_BASE_ADDR 0x118
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#define ACP70_DMA_DESC_MAX_NUM_DSCR 0x11C
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#define ACP70_DMA_CH_STS 0x120
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#define ACP70_DMA_CH_GROUP 0x124
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#define ACP70_DMA_CH_RST_STS 0x128
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/* Registers from ACP_DSP_0 block */
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#define ACP_DSP0_RUNSTALL 0x414
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@ -56,11 +67,13 @@
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#define ACP3X_PGFSM_BASE 0x141C
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#define ACP5X_PGFSM_BASE 0x1424
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#define ACP6X_PGFSM_BASE 0x1024
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#define ACP70_PGFSM_BASE ACP6X_PGFSM_BASE
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#define PGFSM_CONTROL_OFFSET 0x0
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#define PGFSM_STATUS_OFFSET 0x4
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#define ACP3X_CLKMUX_SEL 0x1424
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#define ACP5X_CLKMUX_SEL 0x142C
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#define ACP6X_CLKMUX_SEL 0x102C
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#define ACP70_CLKMUX_SEL ACP6X_CLKMUX_SEL
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/* Registers from ACP_INTR block */
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#define ACP3X_EXT_INTR_STAT 0x1808
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@ -69,22 +82,30 @@
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#define ACP6X_EXTERNAL_INTR_CNTL 0x1A04
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#define ACP6X_EXT_INTR_STAT 0x1A0C
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#define ACP6X_EXT_INTR_STAT1 0x1A10
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#define ACP70_EXTERNAL_INTR_ENB ACP6X_EXTERNAL_INTR_ENB
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#define ACP70_EXTERNAL_INTR_CNTL ACP6X_EXTERNAL_INTR_CNTL
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#define ACP70_EXT_INTR_STAT ACP6X_EXT_INTR_STAT
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#define ACP70_EXT_INTR_STAT1 ACP6X_EXT_INTR_STAT1
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#define ACP3X_DSP_SW_INTR_BASE 0x1814
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#define ACP5X_DSP_SW_INTR_BASE 0x1814
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#define ACP6X_DSP_SW_INTR_BASE 0x1808
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#define ACP70_DSP_SW_INTR_BASE ACP6X_DSP_SW_INTR_BASE
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#define DSP_SW_INTR_CNTL_OFFSET 0x0
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#define DSP_SW_INTR_STAT_OFFSET 0x4
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#define DSP_SW_INTR_TRIG_OFFSET 0x8
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#define ACP3X_ERROR_STATUS 0x18C4
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#define ACP6X_ERROR_STATUS 0x1A4C
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#define ACP70_ERROR_STATUS ACP6X_ERROR_STATUS
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#define ACP3X_AXI2DAGB_SEM_0 0x1880
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#define ACP5X_AXI2DAGB_SEM_0 0x1884
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#define ACP6X_AXI2DAGB_SEM_0 0x1874
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#define ACP70_AXI2DAGB_SEM_0 ACP6X_AXI2DAGB_SEM_0
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/* ACP common registers to report errors related to I2S & SoundWire interfaces */
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#define ACP3X_SW_I2S_ERROR_REASON 0x18C8
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#define ACP6X_SW0_I2S_ERROR_REASON 0x18B4
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#define ACP7X_SW0_I2S_ERROR_REASON ACP6X_SW0_I2S_ERROR_REASON
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#define ACP_SW1_I2S_ERROR_REASON 0x1A50
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/* Registers from ACP_SHA block */
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@ -101,6 +122,7 @@
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#define ACP_SCRATCH_REG_0 0x10000
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#define ACP6X_DSP_FUSION_RUNSTALL 0x0644
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#define ACP70_DSP_FUSION_RUNSTALL ACP6X_DSP_FUSION_RUNSTALL
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/* Cache window registers */
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#define ACP_DSP0_CACHE_OFFSET0 0x0420
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@ -64,13 +64,24 @@ static void init_dma_descriptor(struct acp_dev_data *adata)
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{
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struct snd_sof_dev *sdev = adata->dev;
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const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
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struct acp_dev_data *acp_data = sdev->pdata->hw_pdata;
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unsigned int addr;
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unsigned int acp_dma_desc_base_addr, acp_dma_desc_max_num_dscr;
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addr = desc->sram_pte_offset + sdev->debug_box.offset +
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offsetof(struct scratch_reg_conf, dma_desc);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_BASE_ADDR, addr);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_MAX_NUM_DSCR, ACP_MAX_DESC_CNT);
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switch (acp_data->pci_rev) {
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case ACP70_PCI_ID:
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acp_dma_desc_base_addr = ACP70_DMA_DESC_BASE_ADDR;
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acp_dma_desc_max_num_dscr = ACP70_DMA_DESC_MAX_NUM_DSCR;
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break;
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default:
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acp_dma_desc_base_addr = ACP_DMA_DESC_BASE_ADDR;
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acp_dma_desc_max_num_dscr = ACP_DMA_DESC_MAX_NUM_DSCR;
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}
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_base_addr, addr);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_max_num_dscr, ACP_MAX_DESC_CNT);
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}
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static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx,
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@ -92,29 +103,51 @@ static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch,
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unsigned int idx, unsigned int dscr_count)
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{
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struct snd_sof_dev *sdev = adata->dev;
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struct acp_dev_data *acp_data = sdev->pdata->hw_pdata;
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const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
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unsigned int val, status;
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unsigned int acp_dma_cntl_0, acp_dma_ch_rst_sts, acp_dma_dscr_err_sts_0;
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unsigned int acp_dma_dscr_cnt_0, acp_dma_prio_0, acp_dma_dscr_strt_idx_0;
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int ret;
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32),
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switch (acp_data->pci_rev) {
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case ACP70_PCI_ID:
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acp_dma_cntl_0 = ACP70_DMA_CNTL_0;
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acp_dma_ch_rst_sts = ACP70_DMA_CH_RST_STS;
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acp_dma_dscr_err_sts_0 = ACP70_DMA_ERR_STS_0;
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acp_dma_dscr_cnt_0 = ACP70_DMA_DSCR_CNT_0;
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acp_dma_prio_0 = ACP70_DMA_PRIO_0;
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acp_dma_dscr_strt_idx_0 = ACP70_DMA_DSCR_STRT_IDX_0;
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break;
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default:
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acp_dma_cntl_0 = ACP_DMA_CNTL_0;
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acp_dma_ch_rst_sts = ACP_DMA_CH_RST_STS;
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acp_dma_dscr_err_sts_0 = ACP_DMA_ERR_STS_0;
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acp_dma_dscr_cnt_0 = ACP_DMA_DSCR_CNT_0;
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acp_dma_prio_0 = ACP_DMA_PRIO_0;
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acp_dma_dscr_strt_idx_0 = ACP_DMA_DSCR_STRT_IDX_0;
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}
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32),
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ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN);
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ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_RST_STS, val,
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ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_rst_sts, val,
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val & (1 << ch), ACP_REG_POLL_INTERVAL,
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ACP_REG_POLL_TIMEOUT_US);
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if (ret < 0) {
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status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat);
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val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32));
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val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, acp_dma_dscr_err_sts_0 +
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ch * sizeof(u32));
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dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status);
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return ret;
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}
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, (ACP_DMA_CNTL_0 + ch * sizeof(u32)), 0);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_CNT_0 + ch * sizeof(u32), dscr_count);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_STRT_IDX_0 + ch * sizeof(u32), idx);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_PRIO_0 + ch * sizeof(u32), 0);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), ACP_DMA_CH_RUN);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, (acp_dma_cntl_0 + ch * sizeof(u32)), 0);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_cnt_0 + ch * sizeof(u32), dscr_count);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_strt_idx_0 + ch * sizeof(u32), idx);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_prio_0 + ch * sizeof(u32), 0);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), ACP_DMA_CH_RUN);
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return ret;
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}
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@ -453,6 +486,10 @@ static int acp_power_on(struct snd_sof_dev *sdev)
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acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK;
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acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK;
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break;
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case ACP70_PCI_ID:
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acp_pgfsm_status_mask = ACP70_PGFSM_STATUS_MASK;
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acp_pgfsm_cntl_mask = ACP70_PGFSM_CNTL_POWER_ON_MASK;
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break;
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default:
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return -EINVAL;
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}
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@ -561,8 +598,11 @@ static bool check_acp_sdw_enable_status(struct snd_sof_dev *sdev)
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int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state)
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{
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struct acp_dev_data *acp_data;
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int ret;
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bool enable = false;
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acp_data = sdev->pdata->hw_pdata;
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/* When acp_reset() function is invoked, it will apply ACP SOFT reset and
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* DSP reset. ACP Soft reset sequence will cause all ACP IP registers will
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* be reset to default values which will break the ClockStop Mode functionality.
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@ -577,8 +617,9 @@ int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state)
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dev_err(sdev->dev, "ACP Reset failed\n");
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return ret;
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}
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x00);
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if (acp_data->pci_rev == ACP70_PCI_ID)
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enable = true;
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable);
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return 0;
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}
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@ -29,6 +29,8 @@
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#define ACP3X_PGFSM_STATUS_MASK 0x03
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#define ACP6X_PGFSM_CNTL_POWER_ON_MASK 0x07
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#define ACP6X_PGFSM_STATUS_MASK 0x0F
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#define ACP70_PGFSM_CNTL_POWER_ON_MASK 0x1F
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#define ACP70_PGFSM_STATUS_MASK 0xFF
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#define ACP_POWERED_ON 0x00
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#define ACP_ASSERT_RESET 0x01
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@ -42,6 +44,7 @@
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#define ACP3X_SRAM_PTE_OFFSET 0x02050000
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#define ACP5X_SRAM_PTE_OFFSET 0x02050000
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#define ACP6X_SRAM_PTE_OFFSET 0x03800000
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#define ACP70_SRAM_PTE_OFFSET ACP6X_SRAM_PTE_OFFSET
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#define PAGE_SIZE_4K_ENABLE 0x2
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#define ACP_PAGE_SIZE 0x1000
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#define ACP_DMA_CH_RUN 0x02
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@ -63,17 +66,20 @@
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#define ACP_DRAM_BASE_ADDRESS 0x01000000
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#define ACP_DRAM_PAGE_COUNT 128
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#define ACP_SRAM_BASE_ADDRESS 0x3806000
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#define ACP7X_SRAM_BASE_ADDRESS 0x380C000
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#define ACP_DSP_TO_HOST_IRQ 0x04
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#define ACP_RN_PCI_ID 0x01
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#define ACP_VANGOGH_PCI_ID 0x50
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#define ACP_RMB_PCI_ID 0x6F
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#define ACP63_PCI_ID 0x63
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#define ACP70_PCI_ID 0x70
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#define HOST_BRIDGE_CZN 0x1630
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#define HOST_BRIDGE_VGH 0x1645
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#define HOST_BRIDGE_RMB 0x14B5
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#define HOST_BRIDGE_ACP63 0x14E8
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#define HOST_BRIDGE_ACP70 0x1507
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#define ACP_SHA_STAT 0x8000
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#define ACP_PSP_TIMEOUT_US 1000000
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#define ACP_EXT_INTR_ERROR_STAT 0x20000000
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@ -326,6 +332,9 @@ int sof_rembrandt_ops_init(struct snd_sof_dev *sdev);
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extern struct snd_sof_dsp_ops sof_acp63_ops;
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int sof_acp63_ops_init(struct snd_sof_dev *sdev);
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extern struct snd_sof_dsp_ops sof_acp70_ops;
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int sof_acp70_ops_init(struct snd_sof_dev *sdev);
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struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev);
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/* Machine configuration */
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int snd_amd_acp_find_config(struct pci_dev *pci);
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|
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142
sound/soc/sof/amd/acp70.c
Normal file
142
sound/soc/sof/amd/acp70.c
Normal file
|
|
@ -0,0 +1,142 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
|
||||
//
|
||||
// This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
// redistributing this file, you may do so under either license.
|
||||
//
|
||||
// Copyright(c) 2024 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
|
||||
|
||||
/*
|
||||
* Hardware interface for Audio DSP on ACP7.0 version based platform
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include "../ops.h"
|
||||
#include "../sof-audio.h"
|
||||
#include "acp.h"
|
||||
#include "acp-dsp-offset.h"
|
||||
|
||||
#define I2S_HS_INSTANCE 0
|
||||
#define I2S_BT_INSTANCE 1
|
||||
#define I2S_SP_INSTANCE 2
|
||||
#define PDM_DMIC_INSTANCE 3
|
||||
#define I2S_HS_VIRTUAL_INSTANCE 4
|
||||
|
||||
static struct snd_soc_dai_driver acp70_sof_dai[] = {
|
||||
[I2S_HS_INSTANCE] = {
|
||||
.id = I2S_HS_INSTANCE,
|
||||
.name = "acp-sof-hs",
|
||||
.playback = {
|
||||
.rates = SNDRV_PCM_RATE_8000_96000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
|
||||
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
|
||||
.channels_min = 2,
|
||||
.channels_max = 8,
|
||||
.rate_min = 8000,
|
||||
.rate_max = 96000,
|
||||
},
|
||||
.capture = {
|
||||
.rates = SNDRV_PCM_RATE_8000_48000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
|
||||
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
|
||||
/* Supporting only stereo for I2S HS controller capture */
|
||||
.channels_min = 2,
|
||||
.channels_max = 2,
|
||||
.rate_min = 8000,
|
||||
.rate_max = 48000,
|
||||
},
|
||||
},
|
||||
|
||||
[I2S_BT_INSTANCE] = {
|
||||
.id = I2S_BT_INSTANCE,
|
||||
.name = "acp-sof-bt",
|
||||
.playback = {
|
||||
.rates = SNDRV_PCM_RATE_8000_96000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
|
||||
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
|
||||
.channels_min = 2,
|
||||
.channels_max = 8,
|
||||
.rate_min = 8000,
|
||||
.rate_max = 96000,
|
||||
},
|
||||
.capture = {
|
||||
.rates = SNDRV_PCM_RATE_8000_48000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
|
||||
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
|
||||
/* Supporting only stereo for I2S BT controller capture */
|
||||
.channels_min = 2,
|
||||
.channels_max = 2,
|
||||
.rate_min = 8000,
|
||||
.rate_max = 48000,
|
||||
},
|
||||
},
|
||||
|
||||
[I2S_SP_INSTANCE] = {
|
||||
.id = I2S_SP_INSTANCE,
|
||||
.name = "acp-sof-sp",
|
||||
.playback = {
|
||||
.rates = SNDRV_PCM_RATE_8000_96000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
|
||||
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
|
||||
.channels_min = 2,
|
||||
.channels_max = 8,
|
||||
.rate_min = 8000,
|
||||
.rate_max = 96000,
|
||||
},
|
||||
.capture = {
|
||||
.rates = SNDRV_PCM_RATE_8000_48000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
|
||||
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
|
||||
/* Supporting only stereo for I2S SP controller capture */
|
||||
.channels_min = 2,
|
||||
.channels_max = 2,
|
||||
.rate_min = 8000,
|
||||
.rate_max = 48000,
|
||||
},
|
||||
},
|
||||
|
||||
[PDM_DMIC_INSTANCE] = {
|
||||
.id = PDM_DMIC_INSTANCE,
|
||||
.name = "acp-sof-dmic",
|
||||
.capture = {
|
||||
.rates = SNDRV_PCM_RATE_8000_48000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S32_LE,
|
||||
.channels_min = 2,
|
||||
.channels_max = 4,
|
||||
.rate_min = 8000,
|
||||
.rate_max = 48000,
|
||||
},
|
||||
},
|
||||
|
||||
[I2S_HS_VIRTUAL_INSTANCE] = {
|
||||
.id = I2S_HS_VIRTUAL_INSTANCE,
|
||||
.name = "acp-sof-hs-virtual",
|
||||
.playback = {
|
||||
.rates = SNDRV_PCM_RATE_8000_96000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
|
||||
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
|
||||
.channels_min = 2,
|
||||
.channels_max = 8,
|
||||
.rate_min = 8000,
|
||||
.rate_max = 96000,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* Phoenix ops */
|
||||
struct snd_sof_dsp_ops sof_acp70_ops;
|
||||
EXPORT_SYMBOL_NS(sof_acp70_ops, SND_SOC_SOF_AMD_COMMON);
|
||||
|
||||
int sof_acp70_ops_init(struct snd_sof_dev *sdev)
|
||||
{
|
||||
/* common defaults */
|
||||
memcpy(&sof_acp70_ops, &sof_acp_common_ops, sizeof(struct snd_sof_dsp_ops));
|
||||
|
||||
sof_acp70_ops.drv = acp70_sof_dai;
|
||||
sof_acp70_ops.num_drv = ARRAY_SIZE(acp70_sof_dai);
|
||||
|
||||
return 0;
|
||||
}
|
||||
112
sound/soc/sof/amd/pci-acp70.c
Normal file
112
sound/soc/sof/amd/pci-acp70.c
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
|
||||
//
|
||||
// This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
// redistributing this file, you may do so under either license.
|
||||
//
|
||||
// Copyright(c) 2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
|
||||
|
||||
/*.
|
||||
* PCI interface for ACP7.0 device
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <sound/sof.h>
|
||||
#include <sound/soc-acpi.h>
|
||||
|
||||
#include "../ops.h"
|
||||
#include "../sof-pci-dev.h"
|
||||
#include "../../amd/mach-config.h"
|
||||
#include "acp.h"
|
||||
#include "acp-dsp-offset.h"
|
||||
|
||||
#define ACP70_FUTURE_REG_ACLK_0 0x1854
|
||||
#define ACP70_REG_START 0x1240000
|
||||
#define ACP70_REG_END 0x125C000
|
||||
|
||||
static const struct sof_amd_acp_desc acp70_chip_info = {
|
||||
.host_bridge_id = HOST_BRIDGE_ACP70,
|
||||
.pgfsm_base = ACP70_PGFSM_BASE,
|
||||
.ext_intr_enb = ACP70_EXTERNAL_INTR_ENB,
|
||||
.ext_intr_cntl = ACP70_EXTERNAL_INTR_CNTL,
|
||||
.ext_intr_stat = ACP70_EXT_INTR_STAT,
|
||||
.ext_intr_stat1 = ACP70_EXT_INTR_STAT1,
|
||||
.dsp_intr_base = ACP70_DSP_SW_INTR_BASE,
|
||||
.acp_sw0_i2s_err_reason = ACP7X_SW0_I2S_ERROR_REASON,
|
||||
.sram_pte_offset = ACP70_SRAM_PTE_OFFSET,
|
||||
.hw_semaphore_offset = ACP70_AXI2DAGB_SEM_0,
|
||||
.fusion_dsp_offset = ACP70_DSP_FUSION_RUNSTALL,
|
||||
.probe_reg_offset = ACP70_FUTURE_REG_ACLK_0,
|
||||
.reg_start_addr = ACP70_REG_START,
|
||||
.reg_end_addr = ACP70_REG_END,
|
||||
};
|
||||
|
||||
static const struct sof_dev_desc acp70_desc = {
|
||||
.machines = snd_soc_acpi_amd_acp70_sof_machines,
|
||||
.resindex_lpe_base = 0,
|
||||
.resindex_pcicfg_base = -1,
|
||||
.resindex_imr_base = -1,
|
||||
.irqindex_host_ipc = -1,
|
||||
.chip_info = &acp70_chip_info,
|
||||
.ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
|
||||
.ipc_default = SOF_IPC_TYPE_3,
|
||||
.default_fw_path = {
|
||||
[SOF_IPC_TYPE_3] = "amd/sof",
|
||||
},
|
||||
.default_tplg_path = {
|
||||
[SOF_IPC_TYPE_3] = "amd/sof-tplg",
|
||||
},
|
||||
.default_fw_filename = {
|
||||
[SOF_IPC_TYPE_3] = "sof-acp_7_0.ri",
|
||||
},
|
||||
.nocodec_tplg_filename = "sof-acp.tplg",
|
||||
.ops = &sof_acp70_ops,
|
||||
.ops_init = sof_acp70_ops_init,
|
||||
};
|
||||
|
||||
static int acp70_pci_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
|
||||
{
|
||||
unsigned int flag;
|
||||
|
||||
if (pci->revision != ACP70_PCI_ID)
|
||||
return -ENODEV;
|
||||
|
||||
flag = snd_amd_acp_find_config(pci);
|
||||
if (flag != FLAG_AMD_SOF && flag != FLAG_AMD_SOF_ONLY_DMIC)
|
||||
return -ENODEV;
|
||||
|
||||
return sof_pci_probe(pci, pci_id);
|
||||
};
|
||||
|
||||
static void acp70_pci_remove(struct pci_dev *pci)
|
||||
{
|
||||
sof_pci_remove(pci);
|
||||
}
|
||||
|
||||
/* PCI IDs */
|
||||
static const struct pci_device_id acp70_pci_ids[] = {
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_PCI_DEV_ID),
|
||||
.driver_data = (unsigned long)&acp70_desc},
|
||||
{ 0, }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, acp70_pci_ids);
|
||||
|
||||
/* pci_driver definition */
|
||||
static struct pci_driver snd_sof_pci_amd_acp70_driver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.id_table = acp70_pci_ids,
|
||||
.probe = acp70_pci_probe,
|
||||
.remove = acp70_pci_remove,
|
||||
.driver = {
|
||||
.pm = &sof_pci_pm,
|
||||
},
|
||||
};
|
||||
module_pci_driver(snd_sof_pci_amd_acp70_driver);
|
||||
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
MODULE_DESCRIPTION("ACP70 SOF Driver");
|
||||
MODULE_IMPORT_NS(SND_SOC_SOF_AMD_COMMON);
|
||||
MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);
|
||||
Loading…
Reference in New Issue
Block a user