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pwm: Changes for v6.13-rc1

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This pull request prominently contains a new abstraction for PWM
 waveforms that is more expressive that the legacy one. Compared to the
 old abstraction it contains a duty_offset member instead of polarity.
 This new abstraction is already used in an ADC driver merged into the
 iio tree. So I expect you will get a part of this tree also via the iio
 pull request for 6.13-rc1 (tag pwm/duty_offset-for-6.13-rc1).
 
 Otherwise it's the usual collection of fixes, cleanups and dt doc
 updates.
 
 This time around thanks go to Andy Shevchenko, Clark Wang, Conor Dooley,
 David Lechner, Dimitri Fedrau, Frank Li, Jun Li, Kelvin Zhang, Krzysztof
 Kozlowski, Nuno Sa, Shen Lichuan and Trevor Gamblin for code
 contributions, testing and review.
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Merge tag 'pwm/for-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux

Pull pwm updates from Uwe Kleine-König:
 "This contains a new abstraction for PWM waveforms that is more
  expressive that the legacy one. Compared to the old abstraction it
  contains a duty_offset member instead of polarity. This new
  abstraction is already used in an ADC driver merged into the iio tree.

  The new API requires changes to the lowlevel drivers. For now there
  are two drivers that are converted to the new API (axi-pwmgen and
  stm32). Converted drivers continue to work with the old API. Drivers
  not yet converted only work with the older API.

  Otherwise it's the usual collection of fixes, cleanups and dt doc
  updates.

  This time around thanks go to Andy Shevchenko, Clark Wang, Conor
  Dooley, David Lechner, Dimitri Fedrau, Frank Li, Jun Li, Kelvin Zhang,
  Krzysztof Kozlowski, Nuno Sa, Shen Lichuan and Trevor Gamblin for code
  contributions, testing and review"

* tag 'pwm/for-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux:
  pwm: Assume a disabled PWM to emit a constant inactive output
  pwm: core: export pwm_get_state_hw()
  pwm: core: use device_match_name() instead of strcmp(dev_name(...
  dt-bindings: pwm: adi,axi-pwmgen: Increase #pwm-cells to 3
  pwm: imx27: Use clk_bulk_*() API to simplify clock handling
  pwm: imx27: Workaround of the pwm output bug when decrease the duty cycle
  pwm: axi-pwmgen: Enable FORCE_ALIGN by default
  pwm: axi-pwmgen: Rename 0x10 register
  dt-bindings: pwm: amlogic: Document C3 PWM
  pwm: axi-pwmgen: Create a dedicated function for getting driver data from a chip
  pwm: atmel-tcb: Use min() macro
  pwm: stm32: Fix error checking for a regmap_read() call
  pwm: Add kernel doc for members added to pwm_ops recently
  pwm: Reorder symbols in core.c
  pwm: stm32: Implementation of the waveform callbacks
  pwm: axi-pwmgen: Implementation of the waveform callbacks
  pwm: Add tracing for waveform callbacks
  pwm: Provide new consumer API functions for waveforms
  pwm: New abstraction for PWM waveforms
  pwm: Add more locking
This commit is contained in:
Linus Torvalds 2024-11-20 12:34:22 -08:00
commit 7d75606665
9 changed files with 1571 additions and 495 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml
View File

@ -27,7 +27,7 @@ properties:
maxItems: 1
"#pwm-cells":
const: 2
const: 3
clocks:
maxItems: 1
@ -44,5 +44,5 @@ examples:
compatible = "adi,axi-pwmgen-2.00.a";
reg = <0x44b00000 0x1000>;
clocks = <&spi_clk>;
#pwm-cells = <2>;
#pwm-cells = <3>;
};

1
Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
View File

@ -39,6 +39,7 @@ properties:
- amlogic,meson-s4-pwm
- items:
- enum:
- amlogic,c3-pwm
- amlogic,meson-a1-pwm
- const: amlogic,meson-s4-pwm
- items:

885
drivers/pwm/core.c
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File diff suppressed because it is too large Load Diff

4
drivers/pwm/pwm-atmel-tcb.c
View File

@ -342,8 +342,8 @@ static int atmel_tcb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
return 0;
}
period = state->period < INT_MAX ? state->period : INT_MAX;
duty_cycle = state->duty_cycle < INT_MAX ? state->duty_cycle : INT_MAX;
period = min(state->period, INT_MAX);
duty_cycle = min(state->duty_cycle, INT_MAX);
ret = atmel_tcb_pwm_config(chip, pwm, duty_cycle, period);
if (ret)

199
drivers/pwm/pwm-axi-pwmgen.c
View File

@ -9,7 +9,7 @@
*
* Limitations:
* - The writes to registers for period and duty are shadowed until
* LOAD_CONFIG is written to AXI_PWMGEN_REG_CONFIG, at which point
* LOAD_CONFIG is written to AXI_PWMGEN_REG_RSTN, at which point
* they take effect.
* - Writing LOAD_CONFIG also has the effect of re-synchronizing all
* enabled channels, which could cause glitching on other channels. It
@ -23,6 +23,7 @@
#include <linux/err.h>
#include <linux/fpga/adi-axi-common.h>
#include <linux/io.h>
#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
@ -32,14 +33,16 @@
#define AXI_PWMGEN_REG_ID 0x04
#define AXI_PWMGEN_REG_SCRATCHPAD 0x08
#define AXI_PWMGEN_REG_CORE_MAGIC 0x0C
#define AXI_PWMGEN_REG_CONFIG 0x10
#define AXI_PWMGEN_REG_RSTN 0x10
#define AXI_PWMGEN_REG_RSTN_LOAD_CONFIG BIT(1)
#define AXI_PWMGEN_REG_RSTN_RESET BIT(0)
#define AXI_PWMGEN_REG_NPWM 0x14
#define AXI_PWMGEN_REG_CONFIG 0x18
#define AXI_PWMGEN_REG_CONFIG_FORCE_ALIGN BIT(1)
#define AXI_PWMGEN_CHX_PERIOD(ch) (0x40 + (4 * (ch)))
#define AXI_PWMGEN_CHX_DUTY(ch) (0x80 + (4 * (ch)))
#define AXI_PWMGEN_CHX_OFFSET(ch) (0xC0 + (4 * (ch)))
#define AXI_PWMGEN_REG_CORE_MAGIC_VAL 0x601A3471 /* Identification number to test during setup */
#define AXI_PWMGEN_LOAD_CONFIG BIT(1)
#define AXI_PWMGEN_REG_CONFIG_RESET BIT(0)
struct axi_pwmgen_ddata {
struct regmap *regmap;
@ -53,81 +56,147 @@ static const struct regmap_config axi_pwmgen_regmap_config = {
.max_register = 0xFC,
};
static int axi_pwmgen_apply(struct pwm_chip *chip, struct pwm_device *pwm,
const struct pwm_state *state)
/* This represents a hardware configuration for one channel */
struct axi_pwmgen_waveform {
u32 period_cnt;
u32 duty_cycle_cnt;
u32 duty_offset_cnt;
};
static struct axi_pwmgen_ddata *axi_pwmgen_ddata_from_chip(struct pwm_chip *chip)
{
struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip);
unsigned int ch = pwm->hwpwm;
struct regmap *regmap = ddata->regmap;
u64 period_cnt, duty_cnt;
int ret;
if (state->polarity != PWM_POLARITY_NORMAL)
return -EINVAL;
if (state->enabled) {
period_cnt = mul_u64_u64_div_u64(state->period, ddata->clk_rate_hz, NSEC_PER_SEC);
if (period_cnt > UINT_MAX)
period_cnt = UINT_MAX;
if (period_cnt == 0)
return -EINVAL;
ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), period_cnt);
if (ret)
return ret;
duty_cnt = mul_u64_u64_div_u64(state->duty_cycle, ddata->clk_rate_hz, NSEC_PER_SEC);
if (duty_cnt > UINT_MAX)
duty_cnt = UINT_MAX;
ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), duty_cnt);
if (ret)
return ret;
} else {
ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), 0);
if (ret)
return ret;
ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), 0);
if (ret)
return ret;
}
return regmap_write(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_LOAD_CONFIG);
return pwmchip_get_drvdata(chip);
}
static int axi_pwmgen_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
struct pwm_state *state)
static int axi_pwmgen_round_waveform_tohw(struct pwm_chip *chip,
struct pwm_device *pwm,
const struct pwm_waveform *wf,
void *_wfhw)
{
struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip);
struct axi_pwmgen_waveform *wfhw = _wfhw;
struct axi_pwmgen_ddata *ddata = axi_pwmgen_ddata_from_chip(chip);
if (wf->period_length_ns == 0) {
*wfhw = (struct axi_pwmgen_waveform){
.period_cnt = 0,
.duty_cycle_cnt = 0,
.duty_offset_cnt = 0,
};
} else {
/* With ddata->clk_rate_hz < NSEC_PER_SEC this won't overflow. */
wfhw->period_cnt = min_t(u64,
mul_u64_u32_div(wf->period_length_ns, ddata->clk_rate_hz, NSEC_PER_SEC),
U32_MAX);
if (wfhw->period_cnt == 0) {
/*
* The specified period is too short for the hardware.
* Let's round .duty_cycle down to 0 to get a (somewhat)
* valid result.
*/
wfhw->period_cnt = 1;
wfhw->duty_cycle_cnt = 0;
wfhw->duty_offset_cnt = 0;
} else {
wfhw->duty_cycle_cnt = min_t(u64,
mul_u64_u32_div(wf->duty_length_ns, ddata->clk_rate_hz, NSEC_PER_SEC),
U32_MAX);
wfhw->duty_offset_cnt = min_t(u64,
mul_u64_u32_div(wf->duty_offset_ns, ddata->clk_rate_hz, NSEC_PER_SEC),
U32_MAX);
}
}
dev_dbg(&chip->dev, "pwm#%u: %lld/%lld [+%lld] @%lu -> PERIOD: %08x, DUTY: %08x, OFFSET: %08x\n",
pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns,
ddata->clk_rate_hz, wfhw->period_cnt, wfhw->duty_cycle_cnt, wfhw->duty_offset_cnt);
return 0;
}
static int axi_pwmgen_round_waveform_fromhw(struct pwm_chip *chip, struct pwm_device *pwm,
const void *_wfhw, struct pwm_waveform *wf)
{
const struct axi_pwmgen_waveform *wfhw = _wfhw;
struct axi_pwmgen_ddata *ddata = axi_pwmgen_ddata_from_chip(chip);
wf->period_length_ns = DIV64_U64_ROUND_UP((u64)wfhw->period_cnt * NSEC_PER_SEC,
ddata->clk_rate_hz);
wf->duty_length_ns = DIV64_U64_ROUND_UP((u64)wfhw->duty_cycle_cnt * NSEC_PER_SEC,
ddata->clk_rate_hz);
wf->duty_offset_ns = DIV64_U64_ROUND_UP((u64)wfhw->duty_offset_cnt * NSEC_PER_SEC,
ddata->clk_rate_hz);
return 0;
}
static int axi_pwmgen_write_waveform(struct pwm_chip *chip,
struct pwm_device *pwm,
const void *_wfhw)
{
const struct axi_pwmgen_waveform *wfhw = _wfhw;
struct axi_pwmgen_ddata *ddata = axi_pwmgen_ddata_from_chip(chip);
struct regmap *regmap = ddata->regmap;
unsigned int ch = pwm->hwpwm;
u32 cnt;
int ret;
ret = regmap_read(regmap, AXI_PWMGEN_CHX_PERIOD(ch), &cnt);
ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), wfhw->period_cnt);
if (ret)
return ret;
state->enabled = cnt != 0;
state->period = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz);
ret = regmap_read(regmap, AXI_PWMGEN_CHX_DUTY(ch), &cnt);
ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), wfhw->duty_cycle_cnt);
if (ret)
return ret;
state->duty_cycle = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz);
ret = regmap_write(regmap, AXI_PWMGEN_CHX_OFFSET(ch), wfhw->duty_offset_cnt);
if (ret)
return ret;
state->polarity = PWM_POLARITY_NORMAL;
return regmap_write(regmap, AXI_PWMGEN_REG_RSTN, AXI_PWMGEN_REG_RSTN_LOAD_CONFIG);
}
static int axi_pwmgen_read_waveform(struct pwm_chip *chip,
struct pwm_device *pwm,
void *_wfhw)
{
struct axi_pwmgen_waveform *wfhw = _wfhw;
struct axi_pwmgen_ddata *ddata = axi_pwmgen_ddata_from_chip(chip);
struct regmap *regmap = ddata->regmap;
unsigned int ch = pwm->hwpwm;
int ret;
ret = regmap_read(regmap, AXI_PWMGEN_CHX_PERIOD(ch), &wfhw->period_cnt);
if (ret)
return ret;
ret = regmap_read(regmap, AXI_PWMGEN_CHX_DUTY(ch), &wfhw->duty_cycle_cnt);
if (ret)
return ret;
ret = regmap_read(regmap, AXI_PWMGEN_CHX_OFFSET(ch), &wfhw->duty_offset_cnt);
if (ret)
return ret;
if (wfhw->duty_cycle_cnt > wfhw->period_cnt)
wfhw->duty_cycle_cnt = wfhw->period_cnt;
/* XXX: is this the actual behaviour of the hardware? */
if (wfhw->duty_offset_cnt >= wfhw->period_cnt) {
wfhw->duty_cycle_cnt = 0;
wfhw->duty_offset_cnt = 0;
}
return 0;
}
static const struct pwm_ops axi_pwmgen_pwm_ops = {
.apply = axi_pwmgen_apply,
.get_state = axi_pwmgen_get_state,
.sizeof_wfhw = sizeof(struct axi_pwmgen_waveform),
.round_waveform_tohw = axi_pwmgen_round_waveform_tohw,
.round_waveform_fromhw = axi_pwmgen_round_waveform_fromhw,
.read_waveform = axi_pwmgen_read_waveform,
.write_waveform = axi_pwmgen_write_waveform,
};
static int axi_pwmgen_setup(struct regmap *regmap, struct device *dev)
@ -156,7 +225,17 @@ static int axi_pwmgen_setup(struct regmap *regmap, struct device *dev)
}
/* Enable the core */
ret = regmap_clear_bits(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_REG_CONFIG_RESET);
ret = regmap_clear_bits(regmap, AXI_PWMGEN_REG_RSTN, AXI_PWMGEN_REG_RSTN_RESET);
if (ret)
return ret;
/*
* Enable force align so that changes to PWM period and duty cycle take
* effect immediately. Otherwise, the effect of the change is delayed
* until the period of all channels run out, which can be long after the
* apply function returns.
*/
ret = regmap_set_bits(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_REG_CONFIG_FORCE_ALIGN);
if (ret)
return ret;

161
drivers/pwm/pwm-imx27.c
View File

@ -26,6 +26,7 @@
#define MX3_PWMSR 0x04 /* PWM Status Register */
#define MX3_PWMSAR 0x0C /* PWM Sample Register */
#define MX3_PWMPR 0x10 /* PWM Period Register */
#define MX3_PWMCNR 0x14 /* PWM Counter Register */
#define MX3_PWMCR_FWM GENMASK(27, 26)
#define MX3_PWMCR_STOPEN BIT(25)
@ -79,9 +80,12 @@
/* PWMPR register value of 0xffff has the same effect as 0xfffe */
#define MX3_PWMPR_MAX 0xfffe
static const char * const pwm_imx27_clks[] = {"ipg", "per"};
#define PWM_IMX27_PER 1
struct pwm_imx27_chip {
struct clk *clk_ipg;
struct clk *clk_per;
struct clk_bulk_data clks[ARRAY_SIZE(pwm_imx27_clks)];
int clks_cnt;
void __iomem *mmio_base;
/*
@ -97,29 +101,6 @@ static inline struct pwm_imx27_chip *to_pwm_imx27_chip(struct pwm_chip *chip)
return pwmchip_get_drvdata(chip);
}
static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx)
{
int ret;
ret = clk_prepare_enable(imx->clk_ipg);
if (ret)
return ret;
ret = clk_prepare_enable(imx->clk_per);
if (ret) {
clk_disable_unprepare(imx->clk_ipg);
return ret;
}
return 0;
}
static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx)
{
clk_disable_unprepare(imx->clk_per);
clk_disable_unprepare(imx->clk_ipg);
}
static int pwm_imx27_get_state(struct pwm_chip *chip,
struct pwm_device *pwm, struct pwm_state *state)
{
@ -128,7 +109,7 @@ static int pwm_imx27_get_state(struct pwm_chip *chip,
u64 tmp;
int ret;
ret = pwm_imx27_clk_prepare_enable(imx);
ret = clk_bulk_prepare_enable(imx->clks_cnt, imx->clks);
if (ret < 0)
return ret;
@ -151,7 +132,7 @@ static int pwm_imx27_get_state(struct pwm_chip *chip,
}
prescaler = MX3_PWMCR_PRESCALER_GET(val);
pwm_clk = clk_get_rate(imx->clk_per);
pwm_clk = clk_get_rate(imx->clks[PWM_IMX27_PER].clk);
val = readl(imx->mmio_base + MX3_PWMPR);
period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
@ -171,7 +152,7 @@ static int pwm_imx27_get_state(struct pwm_chip *chip,
tmp = NSEC_PER_SEC * (u64)(val) * prescaler;
state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk);
pwm_imx27_clk_disable_unprepare(imx);
clk_bulk_disable_unprepare(imx->clks_cnt, imx->clks);
return 0;
}
@ -219,14 +200,16 @@ static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip,
static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
const struct pwm_state *state)
{
unsigned long period_cycles, duty_cycles, prescale;
unsigned long period_cycles, duty_cycles, prescale, period_us, tmp;
struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
unsigned long long c;
unsigned long long clkrate;
unsigned long flags;
int val;
int ret;
u32 cr;
clkrate = clk_get_rate(imx->clk_per);
clkrate = clk_get_rate(imx->clks[PWM_IMX27_PER].clk);
c = clkrate * state->period;
do_div(c, NSEC_PER_SEC);
@ -256,14 +239,105 @@ static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
if (pwm->state.enabled) {
pwm_imx27_wait_fifo_slot(chip, pwm);
} else {
ret = pwm_imx27_clk_prepare_enable(imx);
ret = clk_bulk_prepare_enable(imx->clks_cnt, imx->clks);
if (ret)
return ret;
pwm_imx27_sw_reset(chip);
}
writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
val = readl(imx->mmio_base + MX3_PWMPR);
val = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
cr = readl(imx->mmio_base + MX3_PWMCR);
tmp = NSEC_PER_SEC * (u64)(val + 2) * MX3_PWMCR_PRESCALER_GET(cr);
tmp = DIV_ROUND_UP_ULL(tmp, clkrate);
period_us = DIV_ROUND_UP_ULL(tmp, 1000);
/*
* ERR051198:
* PWM: PWM output may not function correctly if the FIFO is empty when
* a new SAR value is programmed
*
* Description:
* When the PWM FIFO is empty, a new value programmed to the PWM Sample
* register (PWM_PWMSAR) will be directly applied even if the current
* timer period has not expired.
*
* If the new SAMPLE value programmed in the PWM_PWMSAR register is
* less than the previous value, and the PWM counter register
* (PWM_PWMCNR) that contains the current COUNT value is greater than
* the new programmed SAMPLE value, the current period will not flip
* the level. This may result in an output pulse with a duty cycle of
* 100%.
*
* Consider a change from
* ________
* / \______/
* ^ * ^
* to
* ____
* / \__________/
* ^ ^
* At the time marked by *, the new write value will be directly applied
* to SAR even the current period is not over if FIFO is empty.
*
* ________ ____________________
* / \______/ \__________/
* ^ ^ * ^ ^
* |<-- old SAR -->| |<-- new SAR -->|
*
* That is the output is active for a whole period.
*
* Workaround:
* Check new SAR less than old SAR and current counter is in errata
* windows, write extra old SAR into FIFO and new SAR will effect at
* next period.
*
* Sometime period is quite long, such as over 1 second. If add old SAR
* into FIFO unconditional, new SAR have to wait for next period. It
* may be too long.
*
* Turn off the interrupt to ensure that not IRQ and schedule happen
* during above operations. If any irq and schedule happen, counter
* in PWM will be out of data and take wrong action.
*
* Add a safety margin 1.5us because it needs some time to complete
* IO write.
*
* Use writel_relaxed() to minimize the interval between two writes to
* the SAR register to increase the fastest PWM frequency supported.
*
* When the PWM period is longer than 2us(or <500kHz), this workaround
* can solve this problem. No software workaround is available if PWM
* period is shorter than IO write. Just try best to fill old data
* into FIFO.
*/
c = clkrate * 1500;
do_div(c, NSEC_PER_SEC);
local_irq_save(flags);
val = FIELD_GET(MX3_PWMSR_FIFOAV, readl_relaxed(imx->mmio_base + MX3_PWMSR));
if (duty_cycles < imx->duty_cycle && (cr & MX3_PWMCR_EN)) {
if (period_us < 2) { /* 2us = 500 kHz */
/* Best effort attempt to fix up >500 kHz case */
udelay(3 * period_us);
writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);
writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);
} else if (val < MX3_PWMSR_FIFOAV_2WORDS) {
val = readl_relaxed(imx->mmio_base + MX3_PWMCNR);
/*
* If counter is close to period, controller may roll over when
* next IO write.
*/
if ((val + c >= duty_cycles && val < imx->duty_cycle) ||
val + c >= period_cycles)
writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);
}
}
writel_relaxed(duty_cycles, imx->mmio_base + MX3_PWMSAR);
local_irq_restore(flags);
writel(period_cycles, imx->mmio_base + MX3_PWMPR);
/*
@ -287,7 +361,7 @@ static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
writel(cr, imx->mmio_base + MX3_PWMCR);
if (!state->enabled)
pwm_imx27_clk_disable_unprepare(imx);
clk_bulk_disable_unprepare(imx->clks_cnt, imx->clks);
return 0;
}
@ -309,21 +383,22 @@ static int pwm_imx27_probe(struct platform_device *pdev)
struct pwm_imx27_chip *imx;
int ret;
u32 pwmcr;
int i;
chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*imx));
if (IS_ERR(chip))
return PTR_ERR(chip);
imx = to_pwm_imx27_chip(chip);
imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
if (IS_ERR(imx->clk_ipg))
return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_ipg),
"getting ipg clock failed\n");
imx->clks_cnt = ARRAY_SIZE(pwm_imx27_clks);
for (i = 0; i < imx->clks_cnt; ++i)
imx->clks[i].id = pwm_imx27_clks[i];
imx->clk_per = devm_clk_get(&pdev->dev, "per");
if (IS_ERR(imx->clk_per))
return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_per),
"failed to get peripheral clock\n");
ret = devm_clk_bulk_get(&pdev->dev, imx->clks_cnt, imx->clks);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"getting clocks failed\n");
chip->ops = &pwm_imx27_ops;
@ -331,14 +406,14 @@ static int pwm_imx27_probe(struct platform_device *pdev)
if (IS_ERR(imx->mmio_base))
return PTR_ERR(imx->mmio_base);
ret = pwm_imx27_clk_prepare_enable(imx);
ret = clk_bulk_prepare_enable(imx->clks_cnt, imx->clks);
if (ret)
return ret;
/* keep clks on if pwm is running */
pwmcr = readl(imx->mmio_base + MX3_PWMCR);
if (!(pwmcr & MX3_PWMCR_EN))
pwm_imx27_clk_disable_unprepare(imx);
clk_bulk_disable_unprepare(imx->clks_cnt, imx->clks);
return devm_pwmchip_add(&pdev->dev, chip);
}

612
drivers/pwm/pwm-stm32.c
View File

@ -51,6 +51,391 @@ static u32 active_channels(struct stm32_pwm *dev)
return ccer & TIM_CCER_CCXE;
}
struct stm32_pwm_waveform {
u32 ccer;
u32 psc;
u32 arr;
u32 ccr;
};
static int stm32_pwm_round_waveform_tohw(struct pwm_chip *chip,
struct pwm_device *pwm,
const struct pwm_waveform *wf,
void *_wfhw)
{
struct stm32_pwm_waveform *wfhw = _wfhw;
struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
unsigned int ch = pwm->hwpwm;
unsigned long rate;
u64 ccr, duty;
int ret;
if (wf->period_length_ns == 0) {
*wfhw = (struct stm32_pwm_waveform){
.ccer = 0,
};
return 0;
}
ret = clk_enable(priv->clk);
if (ret)
return ret;
wfhw->ccer = TIM_CCER_CCxE(ch + 1);
if (priv->have_complementary_output)
wfhw->ccer = TIM_CCER_CCxNE(ch + 1);
rate = clk_get_rate(priv->clk);
if (active_channels(priv) & ~(1 << ch * 4)) {
u64 arr;
/*
* Other channels are already enabled, so the configured PSC and
* ARR must be used for this channel, too.
*/
ret = regmap_read(priv->regmap, TIM_PSC, &wfhw->psc);
if (ret)
goto out;
ret = regmap_read(priv->regmap, TIM_ARR, &wfhw->arr);
if (ret)
goto out;
/*
* calculate the best value for ARR for the given PSC, refuse if
* the resulting period gets bigger than the requested one.
*/
arr = mul_u64_u64_div_u64(wf->period_length_ns, rate,
(u64)NSEC_PER_SEC * (wfhw->psc + 1));
if (arr <= wfhw->arr) {
/*
* requested period is small than the currently
* configured and unchangable period, report back the smallest
* possible period, i.e. the current state; Initialize
* ccr to anything valid.
*/
wfhw->ccr = 0;
ret = 1;
goto out;
}
} else {
/*
* .probe() asserted that clk_get_rate() is not bigger than 1 GHz, so
* the calculations here won't overflow.
* First we need to find the minimal value for prescaler such that
*
* period_ns * clkrate
* ------------------------------ < max_arr + 1
* NSEC_PER_SEC * (prescaler + 1)
*
* This equation is equivalent to
*
* period_ns * clkrate
* ---------------------------- < prescaler + 1
* NSEC_PER_SEC * (max_arr + 1)
*
* Using integer division and knowing that the right hand side is
* integer, this is further equivalent to
*
* (period_ns * clkrate) // (NSEC_PER_SEC * (max_arr + 1)) ≤ prescaler
*/
u64 psc = mul_u64_u64_div_u64(wf->period_length_ns, rate,
(u64)NSEC_PER_SEC * ((u64)priv->max_arr + 1));
u64 arr;
wfhw->psc = min_t(u64, psc, MAX_TIM_PSC);
arr = mul_u64_u64_div_u64(wf->period_length_ns, rate,
(u64)NSEC_PER_SEC * (wfhw->psc + 1));
if (!arr) {
/*
* requested period is too small, report back the smallest
* possible period, i.e. ARR = 0. The only valid CCR
* value is then zero, too.
*/
wfhw->arr = 0;
wfhw->ccr = 0;
ret = 1;
goto out;
}
/*
* ARR is limited intentionally to values less than
* priv->max_arr to allow 100% duty cycle.
*/
wfhw->arr = min_t(u64, arr, priv->max_arr) - 1;
}
duty = mul_u64_u64_div_u64(wf->duty_length_ns, rate,
(u64)NSEC_PER_SEC * (wfhw->psc + 1));
duty = min_t(u64, duty, wfhw->arr + 1);
if (wf->duty_length_ns && wf->duty_offset_ns &&
wf->duty_length_ns + wf->duty_offset_ns >= wf->period_length_ns) {
wfhw->ccer |= TIM_CCER_CCxP(ch + 1);
if (priv->have_complementary_output)
wfhw->ccer |= TIM_CCER_CCxNP(ch + 1);
ccr = wfhw->arr + 1 - duty;
} else {
ccr = duty;
}
wfhw->ccr = min_t(u64, ccr, wfhw->arr + 1);
dev_dbg(&chip->dev, "pwm#%u: %lld/%lld [+%lld] @%lu -> CCER: %08x, PSC: %08x, ARR: %08x, CCR: %08x\n",
pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns,
rate, wfhw->ccer, wfhw->psc, wfhw->arr, wfhw->ccr);
out:
clk_disable(priv->clk);
return ret;
}
/*
* This should be moved to lib/math/div64.c. Currently there are some changes
* pending to mul_u64_u64_div_u64. Uwe will care for that when the dust settles.
*/
static u64 stm32_pwm_mul_u64_u64_div_u64_roundup(u64 a, u64 b, u64 c)
{
u64 res = mul_u64_u64_div_u64(a, b, c);
/* Those multiplications might overflow but it doesn't matter */
u64 rem = a * b - c * res;
if (rem)
res += 1;
return res;
}
static int stm32_pwm_round_waveform_fromhw(struct pwm_chip *chip,
struct pwm_device *pwm,
const void *_wfhw,
struct pwm_waveform *wf)
{
const struct stm32_pwm_waveform *wfhw = _wfhw;
struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
unsigned int ch = pwm->hwpwm;
if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) {
unsigned long rate = clk_get_rate(priv->clk);
u64 ccr_ns;
/* The result doesn't overflow for rate >= 15259 */
wf->period_length_ns = stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1),
NSEC_PER_SEC, rate);
ccr_ns = stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * wfhw->ccr,
NSEC_PER_SEC, rate);
if (wfhw->ccer & TIM_CCER_CCxP(ch + 1)) {
wf->duty_length_ns =
stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1 - wfhw->ccr),
NSEC_PER_SEC, rate);
wf->duty_offset_ns = ccr_ns;
} else {
wf->duty_length_ns = ccr_ns;
wf->duty_offset_ns = 0;
}
dev_dbg(&chip->dev, "pwm#%u: CCER: %08x, PSC: %08x, ARR: %08x, CCR: %08x @%lu -> %lld/%lld [+%lld]\n",
pwm->hwpwm, wfhw->ccer, wfhw->psc, wfhw->arr, wfhw->ccr, rate,
wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns);
} else {
*wf = (struct pwm_waveform){
.period_length_ns = 0,
};
}
return 0;
}
static int stm32_pwm_read_waveform(struct pwm_chip *chip,
struct pwm_device *pwm,
void *_wfhw)
{
struct stm32_pwm_waveform *wfhw = _wfhw;
struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
unsigned int ch = pwm->hwpwm;
int ret;
ret = clk_enable(priv->clk);
if (ret)
return ret;
ret = regmap_read(priv->regmap, TIM_CCER, &wfhw->ccer);
if (ret)
goto out;
if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) {
ret = regmap_read(priv->regmap, TIM_PSC, &wfhw->psc);
if (ret)
goto out;
ret = regmap_read(priv->regmap, TIM_ARR, &wfhw->arr);
if (ret)
goto out;
if (wfhw->arr == U32_MAX)
wfhw->arr -= 1;
ret = regmap_read(priv->regmap, TIM_CCRx(ch + 1), &wfhw->ccr);
if (ret)
goto out;
if (wfhw->ccr > wfhw->arr + 1)
wfhw->ccr = wfhw->arr + 1;
}
out:
clk_disable(priv->clk);
return ret;
}
static int stm32_pwm_write_waveform(struct pwm_chip *chip,
struct pwm_device *pwm,
const void *_wfhw)
{
const struct stm32_pwm_waveform *wfhw = _wfhw;
struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
unsigned int ch = pwm->hwpwm;
int ret;
ret = clk_enable(priv->clk);
if (ret)
return ret;
if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) {
u32 ccer, mask;
unsigned int shift;
u32 ccmr;
ret = regmap_read(priv->regmap, TIM_CCER, &ccer);
if (ret)
goto out;
/* If there are other channels enabled, don't update PSC and ARR */
if (ccer & ~TIM_CCER_CCxE(ch + 1) & TIM_CCER_CCXE) {
u32 psc, arr;
ret = regmap_read(priv->regmap, TIM_PSC, &psc);
if (ret)
goto out;
if (psc != wfhw->psc) {
ret = -EBUSY;
goto out;
}
ret = regmap_read(priv->regmap, TIM_ARR, &arr);
if (ret)
goto out;
if (arr != wfhw->arr) {
ret = -EBUSY;
goto out;
}
} else {
ret = regmap_write(priv->regmap, TIM_PSC, wfhw->psc);
if (ret)
goto out;
ret = regmap_write(priv->regmap, TIM_ARR, wfhw->arr);
if (ret)
goto out;
ret = regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
if (ret)
goto out;
}
/* set polarity */
mask = TIM_CCER_CCxP(ch + 1) | TIM_CCER_CCxNP(ch + 1);
ret = regmap_update_bits(priv->regmap, TIM_CCER, mask, wfhw->ccer);
if (ret)
goto out;
ret = regmap_write(priv->regmap, TIM_CCRx(ch + 1), wfhw->ccr);
if (ret)
goto out;
/* Configure output mode */
shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
mask = CCMR_CHANNEL_MASK << shift;
if (ch < 2)
ret = regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
else
ret = regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
if (ret)
goto out;
ret = regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);
if (ret)
goto out;
if (!(ccer & TIM_CCER_CCxE(ch + 1))) {
mask = TIM_CCER_CCxE(ch + 1) | TIM_CCER_CCxNE(ch + 1);
ret = clk_enable(priv->clk);
if (ret)
goto out;
ccer = (ccer & ~mask) | (wfhw->ccer & mask);
regmap_write(priv->regmap, TIM_CCER, ccer);
/* Make sure that registers are updated */
regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
/* Enable controller */
regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
}
} else {
/* disable channel */
u32 mask, ccer;
mask = TIM_CCER_CCxE(ch + 1);
if (priv->have_complementary_output)
mask |= TIM_CCER_CCxNE(ch + 1);
ret = regmap_read(priv->regmap, TIM_CCER, &ccer);
if (ret)
goto out;
if (ccer & mask) {
ccer = ccer & ~mask;
ret = regmap_write(priv->regmap, TIM_CCER, ccer);
if (ret)
goto out;
if (!(ccer & TIM_CCER_CCXE)) {
/* When all channels are disabled, we can disable the controller */
ret = regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
if (ret)
goto out;
}
clk_disable(priv->clk);
}
}
out:
clk_disable(priv->clk);
return ret;
}
#define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
#define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
#define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
@ -308,228 +693,13 @@ unlock:
return ret;
}
static int stm32_pwm_config(struct stm32_pwm *priv, unsigned int ch,
u64 duty_ns, u64 period_ns)
{
unsigned long long prd, dty;
unsigned long long prescaler;
u32 ccmr, mask, shift;
/*
* .probe() asserted that clk_get_rate() is not bigger than 1 GHz, so
* the calculations here won't overflow.
* First we need to find the minimal value for prescaler such that
*
* period_ns * clkrate
* ------------------------------ < max_arr + 1
* NSEC_PER_SEC * (prescaler + 1)
*
* This equation is equivalent to
*
* period_ns * clkrate
* ---------------------------- < prescaler + 1
* NSEC_PER_SEC * (max_arr + 1)
*
* Using integer division and knowing that the right hand side is
* integer, this is further equivalent to
*
* (period_ns * clkrate) // (NSEC_PER_SEC * (max_arr + 1)) ≤ prescaler
*/
prescaler = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk),
(u64)NSEC_PER_SEC * ((u64)priv->max_arr + 1));
if (prescaler > MAX_TIM_PSC)
return -EINVAL;
prd = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk),
(u64)NSEC_PER_SEC * (prescaler + 1));
if (!prd)
return -EINVAL;
/*
* All channels share the same prescaler and counter so when two
* channels are active at the same time we can't change them
*/
if (active_channels(priv) & ~(1 << ch * 4)) {
u32 psc, arr;
regmap_read(priv->regmap, TIM_PSC, &psc);
regmap_read(priv->regmap, TIM_ARR, &arr);
if ((psc != prescaler) || (arr != prd - 1))
return -EBUSY;
}
regmap_write(priv->regmap, TIM_PSC, prescaler);
regmap_write(priv->regmap, TIM_ARR, prd - 1);
regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
/* Calculate the duty cycles */
dty = mul_u64_u64_div_u64(duty_ns, clk_get_rate(priv->clk),
(u64)NSEC_PER_SEC * (prescaler + 1));
regmap_write(priv->regmap, TIM_CCRx(ch + 1), dty);
/* Configure output mode */
shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
mask = CCMR_CHANNEL_MASK << shift;
if (ch < 2)
regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
else
regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);
return 0;
}
static int stm32_pwm_set_polarity(struct stm32_pwm *priv, unsigned int ch,
enum pwm_polarity polarity)
{
u32 mask;
mask = TIM_CCER_CCxP(ch + 1);
if (priv->have_complementary_output)
mask |= TIM_CCER_CCxNP(ch + 1);
regmap_update_bits(priv->regmap, TIM_CCER, mask,
polarity == PWM_POLARITY_NORMAL ? 0 : mask);
return 0;
}
static int stm32_pwm_enable(struct stm32_pwm *priv, unsigned int ch)
{
u32 mask;
int ret;
ret = clk_enable(priv->clk);
if (ret)
return ret;
/* Enable channel */
mask = TIM_CCER_CCxE(ch + 1);
if (priv->have_complementary_output)
mask |= TIM_CCER_CCxNE(ch + 1);
regmap_set_bits(priv->regmap, TIM_CCER, mask);
/* Make sure that registers are updated */
regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
/* Enable controller */
regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
return 0;
}
static void stm32_pwm_disable(struct stm32_pwm *priv, unsigned int ch)
{
u32 mask;
/* Disable channel */
mask = TIM_CCER_CCxE(ch + 1);
if (priv->have_complementary_output)
mask |= TIM_CCER_CCxNE(ch + 1);
regmap_clear_bits(priv->regmap, TIM_CCER, mask);
/* When all channels are disabled, we can disable the controller */
if (!active_channels(priv))
regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
clk_disable(priv->clk);
}
static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
const struct pwm_state *state)
{
bool enabled;
struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
int ret;
enabled = pwm->state.enabled;
if (!state->enabled) {
if (enabled)
stm32_pwm_disable(priv, pwm->hwpwm);
return 0;
}
if (state->polarity != pwm->state.polarity)
stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
ret = stm32_pwm_config(priv, pwm->hwpwm,
state->duty_cycle, state->period);
if (ret)
return ret;
if (!enabled && state->enabled)
ret = stm32_pwm_enable(priv, pwm->hwpwm);
return ret;
}
static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
const struct pwm_state *state)
{
struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
int ret;
/* protect common prescaler for all active channels */
mutex_lock(&priv->lock);
ret = stm32_pwm_apply(chip, pwm, state);
mutex_unlock(&priv->lock);
return ret;
}
static int stm32_pwm_get_state(struct pwm_chip *chip,
struct pwm_device *pwm, struct pwm_state *state)
{
struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
int ch = pwm->hwpwm;
unsigned long rate;
u32 ccer, psc, arr, ccr;
u64 dty, prd;
int ret;
mutex_lock(&priv->lock);
ret = regmap_read(priv->regmap, TIM_CCER, &ccer);
if (ret)
goto out;
state->enabled = ccer & TIM_CCER_CCxE(ch + 1);
state->polarity = (ccer & TIM_CCER_CCxP(ch + 1)) ?
PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
ret = regmap_read(priv->regmap, TIM_PSC, &psc);
if (ret)
goto out;
ret = regmap_read(priv->regmap, TIM_ARR, &arr);
if (ret)
goto out;
ret = regmap_read(priv->regmap, TIM_CCRx(ch + 1), &ccr);
if (ret)
goto out;
rate = clk_get_rate(priv->clk);
prd = (u64)NSEC_PER_SEC * (psc + 1) * (arr + 1);
state->period = DIV_ROUND_UP_ULL(prd, rate);
dty = (u64)NSEC_PER_SEC * (psc + 1) * ccr;
state->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
out:
mutex_unlock(&priv->lock);
return ret;
}
static const struct pwm_ops stm32pwm_ops = {
.apply = stm32_pwm_apply_locked,
.get_state = stm32_pwm_get_state,
.sizeof_wfhw = sizeof(struct stm32_pwm_waveform),
.round_waveform_tohw = stm32_pwm_round_waveform_tohw,
.round_waveform_fromhw = stm32_pwm_round_waveform_fromhw,
.read_waveform = stm32_pwm_read_waveform,
.write_waveform = stm32_pwm_write_waveform,
.capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
};

66
include/linux/pwm.h
View File

@ -49,6 +49,31 @@ enum {
PWMF_EXPORTED = 1,
};
/**
* struct pwm_waveform - description of a PWM waveform
* @period_length_ns: PWM period
* @duty_length_ns: PWM duty cycle
* @duty_offset_ns: offset of the rising edge from the period's start
*
* This is a representation of a PWM waveform alternative to struct pwm_state
* below. It's more expressive than struct pwm_state as it contains a
* duty_offset_ns and so can represent offsets other than zero (with .polarity =
* PWM_POLARITY_NORMAL) and period - duty_cycle (.polarity =
* PWM_POLARITY_INVERSED).
*
* Note there is no explicit bool for enabled. A "disabled" PWM is represented
* by .period_length_ns = 0. Note further that the behaviour of a "disabled" PWM
* is undefined. Depending on the hardware's capabilities it might drive the
* active or inactive level, go high-z or even continue to toggle.
*
* The unit for all three members is nanoseconds.
*/
struct pwm_waveform {
u64 period_length_ns;
u64 duty_length_ns;
u64 duty_offset_ns;
};
/*
* struct pwm_state - state of a PWM channel
* @period: PWM period (in nanoseconds)
@ -251,6 +276,11 @@ struct pwm_capture {
* @request: optional hook for requesting a PWM
* @free: optional hook for freeing a PWM
* @capture: capture and report PWM signal
* @sizeof_wfhw: size (in bytes) of driver specific waveform presentation
* @round_waveform_tohw: convert a struct pwm_waveform to driver specific presentation
* @round_waveform_fromhw: convert a driver specific waveform presentation to struct pwm_waveform
* @read_waveform: read driver specific waveform presentation from hardware
* @write_waveform: write driver specific waveform presentation to hardware
* @apply: atomically apply a new PWM config
* @get_state: get the current PWM state.
*/
@ -259,6 +289,17 @@ struct pwm_ops {
void (*free)(struct pwm_chip *chip, struct pwm_device *pwm);
int (*capture)(struct pwm_chip *chip, struct pwm_device *pwm,
struct pwm_capture *result, unsigned long timeout);
size_t sizeof_wfhw;
int (*round_waveform_tohw)(struct pwm_chip *chip, struct pwm_device *pwm,
const struct pwm_waveform *wf, void *wfhw);
int (*round_waveform_fromhw)(struct pwm_chip *chip, struct pwm_device *pwm,
const void *wfhw, struct pwm_waveform *wf);
int (*read_waveform)(struct pwm_chip *chip, struct pwm_device *pwm,
void *wfhw);
int (*write_waveform)(struct pwm_chip *chip, struct pwm_device *pwm,
const void *wfhw);
int (*apply)(struct pwm_chip *chip, struct pwm_device *pwm,
const struct pwm_state *state);
int (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm,
@ -275,6 +316,9 @@ struct pwm_ops {
* @of_xlate: request a PWM device given a device tree PWM specifier
* @atomic: can the driver's ->apply() be called in atomic context
* @uses_pwmchip_alloc: signals if pwmchip_allow was used to allocate this chip
* @operational: signals if the chip can be used (or is already deregistered)
* @nonatomic_lock: mutex for nonatomic chips
* @atomic_lock: mutex for atomic chips
* @pwms: array of PWM devices allocated by the framework
*/
struct pwm_chip {
@ -290,6 +334,16 @@ struct pwm_chip {
/* only used internally by the PWM framework */
bool uses_pwmchip_alloc;
bool operational;
union {
/*
* depending on the chip being atomic or not either the mutex or
* the spinlock is used. It protects .operational and
* synchronizes the callbacks in .ops
*/
struct mutex nonatomic_lock;
spinlock_t atomic_lock;
};
struct pwm_device pwms[] __counted_by(npwm);
};
@ -309,9 +363,14 @@ static inline void pwmchip_set_drvdata(struct pwm_chip *chip, void *data)
}
#if IS_ENABLED(CONFIG_PWM)
/* PWM user APIs */
/* PWM consumer APIs */
int pwm_round_waveform_might_sleep(struct pwm_device *pwm, struct pwm_waveform *wf);
int pwm_get_waveform_might_sleep(struct pwm_device *pwm, struct pwm_waveform *wf);
int pwm_set_waveform_might_sleep(struct pwm_device *pwm, const struct pwm_waveform *wf, bool exact);
int pwm_apply_might_sleep(struct pwm_device *pwm, const struct pwm_state *state);
int pwm_apply_atomic(struct pwm_device *pwm, const struct pwm_state *state);
int pwm_get_state_hw(struct pwm_device *pwm, struct pwm_state *state);
int pwm_adjust_config(struct pwm_device *pwm);
/**
@ -436,6 +495,11 @@ static inline int pwm_apply_atomic(struct pwm_device *pwm,
return -EOPNOTSUPP;
}
static inline int pwm_get_state_hw(struct pwm_device *pwm, struct pwm_state *state)
{
return -EOPNOTSUPP;
}
static inline int pwm_adjust_config(struct pwm_device *pwm)
{
return -EOPNOTSUPP;

134
include/trace/events/pwm.h
View File

@ -8,15 +8,135 @@
#include <linux/pwm.h>
#include <linux/tracepoint.h>
#define TP_PROTO_pwm(args...) \
TP_PROTO(struct pwm_device *pwm, args)
#define TP_ARGS_pwm(args...) \
TP_ARGS(pwm, args)
#define TP_STRUCT__entry_pwm(args...) \
TP_STRUCT__entry( \
__field(unsigned int, chipid) \
__field(unsigned int, hwpwm) \
args)
#define TP_fast_assign_pwm(args...) \
TP_fast_assign( \
__entry->chipid = pwm->chip->id; \
__entry->hwpwm = pwm->hwpwm; \
args)
#define TP_printk_pwm(fmt, args...) \
TP_printk("pwmchip%u.%u: " fmt, __entry->chipid, __entry->hwpwm, args)
#define __field_pwmwf(wf) \
__field(u64, wf ## _period_length_ns) \
__field(u64, wf ## _duty_length_ns) \
__field(u64, wf ## _duty_offset_ns) \
#define fast_assign_pwmwf(wf) \
__entry->wf ## _period_length_ns = wf->period_length_ns; \
__entry->wf ## _duty_length_ns = wf->duty_length_ns; \
__entry->wf ## _duty_offset_ns = wf->duty_offset_ns
#define printk_pwmwf_format(wf) \
"%lld/%lld [+%lld]"
#define printk_pwmwf_formatargs(wf) \
__entry->wf ## _duty_length_ns, __entry->wf ## _period_length_ns, __entry->wf ## _duty_offset_ns
TRACE_EVENT(pwm_round_waveform_tohw,
TP_PROTO_pwm(const struct pwm_waveform *wf, void *wfhw, int err),
TP_ARGS_pwm(wf, wfhw, err),
TP_STRUCT__entry_pwm(
__field_pwmwf(wf)
__field(void *, wfhw)
__field(int, err)
),
TP_fast_assign_pwm(
fast_assign_pwmwf(wf);
__entry->wfhw = wfhw;
__entry->err = err;
),
TP_printk_pwm(printk_pwmwf_format(wf) " > %p err=%d",
printk_pwmwf_formatargs(wf), __entry->wfhw, __entry->err)
);
TRACE_EVENT(pwm_round_waveform_fromhw,
TP_PROTO_pwm(const void *wfhw, struct pwm_waveform *wf, int err),
TP_ARGS_pwm(wfhw, wf, err),
TP_STRUCT__entry_pwm(
__field(const void *, wfhw)
__field_pwmwf(wf)
__field(int, err)
),
TP_fast_assign_pwm(
__entry->wfhw = wfhw;
fast_assign_pwmwf(wf);
__entry->err = err;
),
TP_printk_pwm("%p > " printk_pwmwf_format(wf) " err=%d",
__entry->wfhw, printk_pwmwf_formatargs(wf), __entry->err)
);
TRACE_EVENT(pwm_read_waveform,
TP_PROTO_pwm(void *wfhw, int err),
TP_ARGS_pwm(wfhw, err),
TP_STRUCT__entry_pwm(
__field(void *, wfhw)
__field(int, err)
),
TP_fast_assign_pwm(
__entry->wfhw = wfhw;
__entry->err = err;
),
TP_printk_pwm("%p err=%d",
__entry->wfhw, __entry->err)
);
TRACE_EVENT(pwm_write_waveform,
TP_PROTO_pwm(const void *wfhw, int err),
TP_ARGS_pwm(wfhw, err),
TP_STRUCT__entry_pwm(
__field(const void *, wfhw)
__field(int, err)
),
TP_fast_assign_pwm(
__entry->wfhw = wfhw;
__entry->err = err;
),
TP_printk_pwm("%p err=%d",
__entry->wfhw, __entry->err)
);
DECLARE_EVENT_CLASS(pwm,
TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state, int err),
TP_ARGS(pwm, state, err),
TP_STRUCT__entry(
__field(unsigned int, chipid)
__field(unsigned int, hwpwm)
TP_STRUCT__entry_pwm(
__field(u64, period)
__field(u64, duty_cycle)
__field(enum pwm_polarity, polarity)
@ -24,9 +144,7 @@ DECLARE_EVENT_CLASS(pwm,
__field(int, err)
),
TP_fast_assign(
__entry->chipid = pwm->chip->id;
__entry->hwpwm = pwm->hwpwm;
TP_fast_assign_pwm(
__entry->period = state->period;
__entry->duty_cycle = state->duty_cycle;
__entry->polarity = state->polarity;
@ -34,8 +152,8 @@ DECLARE_EVENT_CLASS(pwm,
__entry->err = err;
),
TP_printk("pwmchip%u.%u: period=%llu duty_cycle=%llu polarity=%d enabled=%d err=%d",
__entry->chipid, __entry->hwpwm, __entry->period, __entry->duty_cycle,
TP_printk_pwm("period=%llu duty_cycle=%llu polarity=%d enabled=%d err=%d",
__entry->period, __entry->duty_cycle,
__entry->polarity, __entry->enabled, __entry->err)
);