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drm/tegra: Add Tegra114 HDMI support
Tegra114 TMDS configuration requires a new peak_current field and the driver current override bit has changed position. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Mikko Perttunen
Thierry Reding
parent
59af0595f4
commit
7d1d28aca0
@ -489,6 +489,7 @@ static const struct of_device_id host1x_drm_subdevs[] = {
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{ .compatible = "nvidia,tegra30-dc", },
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{ .compatible = "nvidia,tegra30-hdmi", },
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{ .compatible = "nvidia,tegra30-gr2d", },
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{ .compatible = "nvidia,tegra114-hdmi", },
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{ /* sentinel */ }
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};
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@ -23,6 +23,7 @@ struct tmds_config {
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u32 pll1;
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u32 pe_current;
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u32 drive_current;
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u32 peak_current;
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};
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struct tegra_hdmi_config {
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@ -31,6 +32,8 @@ struct tegra_hdmi_config {
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unsigned long fuse_override_offset;
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unsigned long fuse_override_value;
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bool has_sor_io_peak_current;
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};
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struct tegra_hdmi {
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@ -233,6 +236,85 @@ static const struct tmds_config tegra30_tmds_config[] = {
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},
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};
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static const struct tmds_config tegra114_tmds_config[] = {
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{ /* 480p/576p / 25.2MHz/27MHz modes */
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.pclk = 27000000,
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.pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
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SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
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.pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
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.pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
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PE_CURRENT1(PE_CURRENT_0_mA_T114) |
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PE_CURRENT2(PE_CURRENT_0_mA_T114) |
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PE_CURRENT3(PE_CURRENT_0_mA_T114),
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.drive_current =
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DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
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DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
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DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
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DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
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.peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
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}, { /* 720p / 74.25MHz modes */
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.pclk = 74250000,
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.pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
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SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
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.pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
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SOR_PLL_TMDS_TERMADJ(0),
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.pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
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PE_CURRENT1(PE_CURRENT_15_mA_T114) |
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PE_CURRENT2(PE_CURRENT_15_mA_T114) |
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PE_CURRENT3(PE_CURRENT_15_mA_T114),
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.drive_current =
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DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
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DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
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DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
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DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
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.peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
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}, { /* 1080p / 148.5MHz modes */
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.pclk = 148500000,
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.pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
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SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
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.pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
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SOR_PLL_TMDS_TERMADJ(0),
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.pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
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PE_CURRENT1(PE_CURRENT_10_mA_T114) |
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PE_CURRENT2(PE_CURRENT_10_mA_T114) |
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PE_CURRENT3(PE_CURRENT_10_mA_T114),
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.drive_current =
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DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
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DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
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DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
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DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
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.peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
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}, { /* 225/297MHz modes */
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.pclk = UINT_MAX,
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.pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
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SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
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.pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
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| SOR_PLL_TMDS_TERM_ENABLE,
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.pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
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PE_CURRENT1(PE_CURRENT_0_mA_T114) |
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PE_CURRENT2(PE_CURRENT_0_mA_T114) |
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PE_CURRENT3(PE_CURRENT_0_mA_T114),
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.drive_current =
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DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
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DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
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DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
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DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
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.peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
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PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
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PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
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PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
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},
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};
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static const struct tegra_hdmi_audio_config *
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tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
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{
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@ -586,6 +668,10 @@ static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
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value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
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value |= hdmi->config->fuse_override_value;
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tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
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if (hdmi->config->has_sor_io_peak_current)
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tegra_hdmi_writel(hdmi, tmds->peak_current,
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HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
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}
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static int tegra_output_hdmi_enable(struct tegra_output *output)
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@ -1052,6 +1138,7 @@ static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
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DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
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DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
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DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
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DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
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#undef DUMP_REG
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@ -1181,6 +1268,7 @@ static const struct tegra_hdmi_config tegra20_hdmi_config = {
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.num_tmds = ARRAY_SIZE(tegra20_tmds_config),
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.fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
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.fuse_override_value = 1 << 31,
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.has_sor_io_peak_current = false,
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};
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static const struct tegra_hdmi_config tegra30_hdmi_config = {
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@ -1188,9 +1276,19 @@ static const struct tegra_hdmi_config tegra30_hdmi_config = {
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.num_tmds = ARRAY_SIZE(tegra30_tmds_config),
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.fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
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.fuse_override_value = 1 << 31,
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.has_sor_io_peak_current = false,
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};
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static const struct tegra_hdmi_config tegra114_hdmi_config = {
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.tmds = tegra114_tmds_config,
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.num_tmds = ARRAY_SIZE(tegra114_tmds_config),
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.fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
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.fuse_override_value = 1 << 31,
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.has_sor_io_peak_current = true,
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};
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static const struct of_device_id tegra_hdmi_of_match[] = {
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{ .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
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{ .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
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{ .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
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{ },
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@ -233,6 +233,10 @@
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#define DRIVE_CURRENT_LANE1(x) (((x) & 0x3f) << 8)
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#define DRIVE_CURRENT_LANE2(x) (((x) & 0x3f) << 16)
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#define DRIVE_CURRENT_LANE3(x) (((x) & 0x3f) << 24)
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#define DRIVE_CURRENT_LANE0_T114(x) (((x) & 0x7f) << 0)
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#define DRIVE_CURRENT_LANE1_T114(x) (((x) & 0x7f) << 8)
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#define DRIVE_CURRENT_LANE2_T114(x) (((x) & 0x7f) << 16)
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#define DRIVE_CURRENT_LANE3_T114(x) (((x) & 0x7f) << 24)
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#define DRIVE_CURRENT_1_500_mA 0x00
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#define DRIVE_CURRENT_1_875_mA 0x01
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@ -298,6 +302,79 @@
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#define DRIVE_CURRENT_24_375_mA 0x3d
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#define DRIVE_CURRENT_24_750_mA 0x3e
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#define DRIVE_CURRENT_0_000_mA_T114 0x00
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#define DRIVE_CURRENT_0_400_mA_T114 0x01
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#define DRIVE_CURRENT_0_800_mA_T114 0x02
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#define DRIVE_CURRENT_1_200_mA_T114 0x03
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#define DRIVE_CURRENT_1_600_mA_T114 0x04
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#define DRIVE_CURRENT_2_000_mA_T114 0x05
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#define DRIVE_CURRENT_2_400_mA_T114 0x06
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#define DRIVE_CURRENT_2_800_mA_T114 0x07
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#define DRIVE_CURRENT_3_200_mA_T114 0x08
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#define DRIVE_CURRENT_3_600_mA_T114 0x09
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#define DRIVE_CURRENT_4_000_mA_T114 0x0a
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#define DRIVE_CURRENT_4_400_mA_T114 0x0b
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#define DRIVE_CURRENT_4_800_mA_T114 0x0c
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#define DRIVE_CURRENT_5_200_mA_T114 0x0d
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#define DRIVE_CURRENT_5_600_mA_T114 0x0e
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#define DRIVE_CURRENT_6_000_mA_T114 0x0f
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#define DRIVE_CURRENT_6_400_mA_T114 0x10
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#define DRIVE_CURRENT_6_800_mA_T114 0x11
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#define DRIVE_CURRENT_7_200_mA_T114 0x12
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#define DRIVE_CURRENT_7_600_mA_T114 0x13
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#define DRIVE_CURRENT_8_000_mA_T114 0x14
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#define DRIVE_CURRENT_8_400_mA_T114 0x15
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#define DRIVE_CURRENT_8_800_mA_T114 0x16
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#define DRIVE_CURRENT_9_200_mA_T114 0x17
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#define DRIVE_CURRENT_9_600_mA_T114 0x18
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#define DRIVE_CURRENT_10_000_mA_T114 0x19
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#define DRIVE_CURRENT_10_400_mA_T114 0x1a
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#define DRIVE_CURRENT_10_800_mA_T114 0x1b
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#define DRIVE_CURRENT_11_200_mA_T114 0x1c
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#define DRIVE_CURRENT_11_600_mA_T114 0x1d
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#define DRIVE_CURRENT_12_000_mA_T114 0x1e
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#define DRIVE_CURRENT_12_400_mA_T114 0x1f
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#define DRIVE_CURRENT_12_800_mA_T114 0x20
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#define DRIVE_CURRENT_13_200_mA_T114 0x21
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#define DRIVE_CURRENT_13_600_mA_T114 0x22
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#define DRIVE_CURRENT_14_000_mA_T114 0x23
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#define DRIVE_CURRENT_14_400_mA_T114 0x24
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#define DRIVE_CURRENT_14_800_mA_T114 0x25
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#define DRIVE_CURRENT_15_200_mA_T114 0x26
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#define DRIVE_CURRENT_15_600_mA_T114 0x27
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#define DRIVE_CURRENT_16_000_mA_T114 0x28
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#define DRIVE_CURRENT_16_400_mA_T114 0x29
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#define DRIVE_CURRENT_16_800_mA_T114 0x2a
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#define DRIVE_CURRENT_17_200_mA_T114 0x2b
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#define DRIVE_CURRENT_17_600_mA_T114 0x2c
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#define DRIVE_CURRENT_18_000_mA_T114 0x2d
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#define DRIVE_CURRENT_18_400_mA_T114 0x2e
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#define DRIVE_CURRENT_18_800_mA_T114 0x2f
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#define DRIVE_CURRENT_19_200_mA_T114 0x30
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#define DRIVE_CURRENT_19_600_mA_T114 0x31
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#define DRIVE_CURRENT_20_000_mA_T114 0x32
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#define DRIVE_CURRENT_20_400_mA_T114 0x33
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#define DRIVE_CURRENT_20_800_mA_T114 0x34
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#define DRIVE_CURRENT_21_200_mA_T114 0x35
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#define DRIVE_CURRENT_21_600_mA_T114 0x36
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#define DRIVE_CURRENT_22_000_mA_T114 0x37
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#define DRIVE_CURRENT_22_400_mA_T114 0x38
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#define DRIVE_CURRENT_22_800_mA_T114 0x39
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#define DRIVE_CURRENT_23_200_mA_T114 0x3a
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#define DRIVE_CURRENT_23_600_mA_T114 0x3b
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#define DRIVE_CURRENT_24_000_mA_T114 0x3c
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#define DRIVE_CURRENT_24_400_mA_T114 0x3d
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#define DRIVE_CURRENT_24_800_mA_T114 0x3e
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#define DRIVE_CURRENT_25_200_mA_T114 0x3f
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#define DRIVE_CURRENT_25_400_mA_T114 0x40
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#define DRIVE_CURRENT_25_800_mA_T114 0x41
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#define DRIVE_CURRENT_26_200_mA_T114 0x42
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#define DRIVE_CURRENT_26_600_mA_T114 0x43
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#define DRIVE_CURRENT_27_000_mA_T114 0x44
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#define DRIVE_CURRENT_27_400_mA_T114 0x45
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#define DRIVE_CURRENT_27_800_mA_T114 0x46
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#define DRIVE_CURRENT_28_200_mA_T114 0x47
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#define HDMI_NV_PDISP_AUDIO_DEBUG0 0x7f
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#define HDMI_NV_PDISP_AUDIO_DEBUG1 0x80
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#define HDMI_NV_PDISP_AUDIO_DEBUG2 0x81
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@ -357,6 +434,23 @@
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#define PE_CURRENT_7_0_mA 0xe
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#define PE_CURRENT_7_5_mA 0xf
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#define PE_CURRENT_0_mA_T114 0x0
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#define PE_CURRENT_1_mA_T114 0x1
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#define PE_CURRENT_2_mA_T114 0x2
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#define PE_CURRENT_3_mA_T114 0x3
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#define PE_CURRENT_4_mA_T114 0x4
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#define PE_CURRENT_5_mA_T114 0x5
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#define PE_CURRENT_6_mA_T114 0x6
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#define PE_CURRENT_7_mA_T114 0x7
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#define PE_CURRENT_8_mA_T114 0x8
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#define PE_CURRENT_9_mA_T114 0x9
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#define PE_CURRENT_10_mA_T114 0xa
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#define PE_CURRENT_11_mA_T114 0xb
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#define PE_CURRENT_12_mA_T114 0xc
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#define PE_CURRENT_13_mA_T114 0xd
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#define PE_CURRENT_14_mA_T114 0xe
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#define PE_CURRENT_15_mA_T114 0xf
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#define HDMI_NV_PDISP_KEY_CTRL 0x9a
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#define HDMI_NV_PDISP_KEY_DEBUG0 0x9b
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#define HDMI_NV_PDISP_KEY_DEBUG1 0x9c
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@ -382,4 +476,61 @@
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#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 0xc5
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#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0xc5
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#define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT 0xd1
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#define PEAK_CURRENT_LANE0(x) (((x) & 0x7f) << 0)
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#define PEAK_CURRENT_LANE1(x) (((x) & 0x7f) << 8)
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#define PEAK_CURRENT_LANE2(x) (((x) & 0x7f) << 16)
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#define PEAK_CURRENT_LANE3(x) (((x) & 0x7f) << 24)
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#define PEAK_CURRENT_0_000_mA 0x00
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#define PEAK_CURRENT_0_200_mA 0x01
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#define PEAK_CURRENT_0_400_mA 0x02
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#define PEAK_CURRENT_0_600_mA 0x03
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#define PEAK_CURRENT_0_800_mA 0x04
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#define PEAK_CURRENT_1_000_mA 0x05
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#define PEAK_CURRENT_1_200_mA 0x06
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#define PEAK_CURRENT_1_400_mA 0x07
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#define PEAK_CURRENT_1_600_mA 0x08
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#define PEAK_CURRENT_1_800_mA 0x09
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#define PEAK_CURRENT_2_000_mA 0x0a
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#define PEAK_CURRENT_2_200_mA 0x0b
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#define PEAK_CURRENT_2_400_mA 0x0c
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#define PEAK_CURRENT_2_600_mA 0x0d
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#define PEAK_CURRENT_2_800_mA 0x0e
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#define PEAK_CURRENT_3_000_mA 0x0f
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#define PEAK_CURRENT_3_200_mA 0x10
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#define PEAK_CURRENT_3_400_mA 0x11
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#define PEAK_CURRENT_3_600_mA 0x12
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#define PEAK_CURRENT_3_800_mA 0x13
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#define PEAK_CURRENT_4_000_mA 0x14
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#define PEAK_CURRENT_4_200_mA 0x15
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#define PEAK_CURRENT_4_400_mA 0x16
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#define PEAK_CURRENT_4_600_mA 0x17
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#define PEAK_CURRENT_4_800_mA 0x18
|
||||
#define PEAK_CURRENT_5_000_mA 0x19
|
||||
#define PEAK_CURRENT_5_200_mA 0x1a
|
||||
#define PEAK_CURRENT_5_400_mA 0x1b
|
||||
#define PEAK_CURRENT_5_600_mA 0x1c
|
||||
#define PEAK_CURRENT_5_800_mA 0x1d
|
||||
#define PEAK_CURRENT_6_000_mA 0x1e
|
||||
#define PEAK_CURRENT_6_200_mA 0x1f
|
||||
#define PEAK_CURRENT_6_400_mA 0x20
|
||||
#define PEAK_CURRENT_6_600_mA 0x21
|
||||
#define PEAK_CURRENT_6_800_mA 0x22
|
||||
#define PEAK_CURRENT_7_000_mA 0x23
|
||||
#define PEAK_CURRENT_7_200_mA 0x24
|
||||
#define PEAK_CURRENT_7_400_mA 0x25
|
||||
#define PEAK_CURRENT_7_600_mA 0x26
|
||||
#define PEAK_CURRENT_7_800_mA 0x27
|
||||
#define PEAK_CURRENT_8_000_mA 0x28
|
||||
#define PEAK_CURRENT_8_200_mA 0x29
|
||||
#define PEAK_CURRENT_8_400_mA 0x2a
|
||||
#define PEAK_CURRENT_8_600_mA 0x2b
|
||||
#define PEAK_CURRENT_8_800_mA 0x2c
|
||||
#define PEAK_CURRENT_9_000_mA 0x2d
|
||||
#define PEAK_CURRENT_9_200_mA 0x2e
|
||||
#define PEAK_CURRENT_9_400_mA 0x2f
|
||||
|
||||
#define HDMI_NV_PDISP_SOR_PAD_CTLS0 0xd2
|
||||
|
||||
#endif /* TEGRA_HDMI_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user