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ath9k_hw: add register definitions for the new ANI
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -114,6 +114,10 @@
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#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
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#define AR_PHY_FIND_SIG_FIRPWR_S 18
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#define AR_PHY_FIND_SIG_LOW 0x9840
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#define AR_PHY_FIND_SIG_FIRSTEP_LOW 0x00000FC0L
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#define AR_PHY_FIND_SIG_FIRSTEP_LOW_S 6
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#define AR_PHY_AGC_CTL1 0x985C
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#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
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#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
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@ -325,6 +329,9 @@
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#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
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#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
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#define AR_PHY_EXT_CCA_THRESH62_S 16
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#define AR_PHY_EXT_TIMING5_CYCPWR_THR1 0x0000FE00L
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#define AR_PHY_EXT_TIMING5_CYCPWR_THR1_S 9
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#define AR_PHY_EXT_MINCCA_PWR 0xFF800000
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#define AR_PHY_EXT_MINCCA_PWR_S 23
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#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
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@ -149,6 +149,8 @@
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#define AR_PHY_EXT_CCA_THRESH62_S 16
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#define AR_PHY_EXT_MINCCA_PWR 0x01FF0000
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#define AR_PHY_EXT_MINCCA_PWR_S 16
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#define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L
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#define AR_PHY_EXT_CYCPWR_THR1_S 9
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#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
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#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
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#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001
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@ -283,6 +285,12 @@
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#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00
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#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9
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#define AR_PHY_MRC_CCK_CTRL (AR_AGC_BASE + 0x1d0)
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#define AR_PHY_MRC_CCK_ENABLE 0x00000001
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#define AR_PHY_MRC_CCK_ENABLE_S 0
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#define AR_PHY_MRC_CCK_MUX_REG 0x00000002
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#define AR_PHY_MRC_CCK_MUX_REG_S 1
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#define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200)
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#define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110
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