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ACPICA: CXL 2.0: CEDT: Add new CEDT table
ACPICA commit 0b03aa8ebd7a5b2b9407893f123ee587af45926f This sets up all of the boilerplate without actually doing anything. Link: https://github.com/acpica/acpica/commit/0b03aa8e Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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@ -28,6 +28,7 @@
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#define ACPI_SIG_BERT "BERT" /* Boot Error Record Table */
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#define ACPI_SIG_BGRT "BGRT" /* Boot Graphics Resource Table */
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#define ACPI_SIG_BOOT "BOOT" /* Simple Boot Flag Table */
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#define ACPI_SIG_CEDT "CEDT" /* CXL Early Discovery Table */
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#define ACPI_SIG_CPEP "CPEP" /* Corrected Platform Error Polling table */
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#define ACPI_SIG_CSRT "CSRT" /* Core System Resource Table */
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#define ACPI_SIG_DBG2 "DBG2" /* Debug Port table type 2 */
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@ -301,6 +302,48 @@ struct acpi_table_boot {
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u8 reserved[3];
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};
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/*******************************************************************************
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*
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* CEDT - CXL Early Discovery Table
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* Version 1
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*
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* Conforms to the "CXL Early Discovery Table" (CXL 2.0)
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*
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******************************************************************************/
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struct acpi_table_cedt {
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struct acpi_table_header header; /* Common ACPI table header */
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};
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/* CEDT subtable header (Performance Record Structure) */
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struct acpi_cedt_header {
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u8 type;
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u8 reserved;
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u16 length;
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};
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/* Values for Type field above */
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enum acpi_cedt_type {
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ACPI_CEDT_TYPE_CHBS = 0,
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};
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/*
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* CEDT subtables
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*/
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/* 0: CXL Host Bridge Structure */
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struct acpi_cedt_chbs {
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ACPI_CEDT_HEADER header;
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u32 uid;
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u32 cxl_version;
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u32 reserved;
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u64 base;
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u64 length;
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};
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/*******************************************************************************
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*
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* CPEP - Corrected Platform Error Polling table (ACPI 4.0)
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