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parisc architecture fixes for kernel v6.0-rc6:
* Allow to configure for 64-bit kernel with ARCH=parisc * Fix asm/errno.h includes in tools directory for parisc and xtensa * Clean up iosapic memory allocation * Minor typo and spelling fixes -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCYydbwQAKCRD3ErUQojoP X0JNAQD050ybcW5iTIs1Hns/20BmpPyI+ph75iNE5jRX/85i/wD8DdfUkI06sfzq vIshpSaXY5AuBNQsblXJpiFCjbU4/Q4= =TCpO -----END PGP SIGNATURE----- Merge tag 'parisc-for-6.0-3' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux Pull parisc architecture fixes from Helge Deller: "Some small parisc architecture fixes for 6.0-rc6: One patch lightens up a previous commit and thus unbreaks building the debian kernel, which tries to configure a 64-bit kernel with the ARCH=parisc environment variable set. The other patches fixes asm/errno.h includes in the tools directory and cleans up memory allocation in the iosapic driver. Summary: - Allow configuring 64-bit kernel with ARCH=parisc - Fix asm/errno.h includes in tools directory for parisc and xtensa - Clean up iosapic memory allocation - Minor typo and spelling fixes" * tag 'parisc-for-6.0-3' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux: parisc: Allow CONFIG_64BIT with ARCH=parisc parisc: remove obsolete manual allocation aligning in iosapic tools/include/uapi: Fix <asm/errno.h> for parisc and xtensa Input: hp_sdc: fix spelling typo in comment parisc: ccio-dma: Add missing iounmap in error path in ccio_probe()
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7c18b453ef
@ -224,8 +224,18 @@ config MLONGCALLS
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Enabling this option will probably slow down your kernel.
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config 64BIT
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def_bool "$(ARCH)" = "parisc64"
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def_bool y if "$(ARCH)" = "parisc64"
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bool "64-bit kernel" if "$(ARCH)" = "parisc"
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depends on PA8X00
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help
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Enable this if you want to support 64bit kernel on PA-RISC platform.
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At the moment, only people willing to use more than 2GB of RAM,
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or having a 64bit-only capable PA-RISC machine should say Y here.
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Since there is no 64bit userland on PA-RISC, there is no point to
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enable this option otherwise. The 64bit kernel is significantly bigger
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and slower than the 32bit one.
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choice
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prompt "Kernel page size"
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@ -1546,6 +1546,7 @@ static int __init ccio_probe(struct parisc_device *dev)
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}
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ccio_ioc_init(ioc);
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if (ccio_init_resources(ioc)) {
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iounmap(ioc->ioc_regs);
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kfree(ioc);
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return -ENOMEM;
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}
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@ -221,16 +221,7 @@ static size_t irt_num_entry;
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static struct irt_entry *iosapic_alloc_irt(int num_entries)
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{
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unsigned long a;
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/* The IRT needs to be 8-byte aligned for the PDC call.
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* Normally kmalloc would guarantee larger alignment, but
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* if CONFIG_DEBUG_SLAB is enabled, then we can get only
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* 4-byte alignment on 32-bit kernels
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*/
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a = (unsigned long)kmalloc(sizeof(struct irt_entry) * num_entries + 8, GFP_KERNEL);
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a = (a + 7UL) & ~7UL;
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return (struct irt_entry *)a;
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return kcalloc(num_entries, sizeof(struct irt_entry), GFP_KERNEL);
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}
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/**
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@ -180,7 +180,7 @@ switch (val) { \
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#define HP_SDC_CMD_SET_IM 0x40 /* 010xxxxx == set irq mask */
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/* The documents provided do not explicitly state that all registers betweem
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/* The documents provided do not explicitly state that all registers between
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* 0x01 and 0x1f inclusive can be read by sending their register index as a
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* command, but this is implied and appears to be the case.
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*/
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@ -9,8 +9,8 @@
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#include "../../../arch/alpha/include/uapi/asm/errno.h"
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#elif defined(__mips__)
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#include "../../../arch/mips/include/uapi/asm/errno.h"
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#elif defined(__xtensa__)
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#include "../../../arch/xtensa/include/uapi/asm/errno.h"
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#elif defined(__hppa__)
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#include "../../../arch/parisc/include/uapi/asm/errno.h"
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#else
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#include <asm-generic/errno.h>
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#endif
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