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blackfin: bf60x: make clock changeable in kernel menuconfig
Add clock changeable support in kernel menuconfig for bf60x. Signed-off-by: Bob Liu <lliubbo@gmail.com>
This commit is contained in:
Bob Liu
parent
1c40093976
commit
7c141c1c5c
@ -435,7 +435,7 @@ config BFIN_KERNEL_CLOCK
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config PLL_BYPASS
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bool "Bypass PLL"
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depends on BFIN_KERNEL_CLOCK
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depends on BFIN_KERNEL_CLOCK && (!BF60x)
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default n
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config CLKIN_HALF
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@ -454,7 +454,7 @@ config VCO_MULT
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default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
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default "22" if BFIN533_BLUETECHNIX_CM
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default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
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default "20" if BFIN561_EZKIT
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default "20" if (BFIN561_EZKIT || BF609)
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default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
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default "25" if BFIN527_AD7160EVAL
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help
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@ -486,12 +486,45 @@ config SCLK_DIV
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int "System Clock Divider"
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depends on BFIN_KERNEL_CLOCK
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range 1 15
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default 5
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default 4
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help
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This sets the frequency of the system clock (including SDRAM or DDR).
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This sets the frequency of the system clock (including SDRAM or DDR) on
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!BF60x else it set the clock for system buses and provides the
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source from which SCLK0 and SCLK1 are derived.
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This can be between 1 and 15
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System Clock = (PLL frequency) / (this setting)
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config SCLK0_DIV
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int "System Clock0 Divider"
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depends on BFIN_KERNEL_CLOCK && BF60x
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range 1 15
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default 1
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help
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This sets the frequency of the system clock0 for PVP and all other
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peripherals not clocked by SCLK1.
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This can be between 1 and 15
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System Clock0 = (System Clock) / (this setting)
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config SCLK1_DIV
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int "System Clock1 Divider"
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depends on BFIN_KERNEL_CLOCK && BF60x
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range 1 15
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default 1
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help
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This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
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This can be between 1 and 15
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System Clock1 = (System Clock) / (this setting)
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config DCLK_DIV
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int "DDR Clock Divider"
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depends on BFIN_KERNEL_CLOCK && BF60x
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range 1 15
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default 2
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help
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This sets the frequency of the DDR memory.
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This can be between 1 and 15
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DDR Clock = (PLL frequency) / (this setting)
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choice
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prompt "DDR SDRAM Chip Type"
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depends on BFIN_KERNEL_CLOCK
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@ -507,7 +540,7 @@ endchoice
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choice
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prompt "DDR/SDRAM Timing"
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depends on BFIN_KERNEL_CLOCK
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depends on BFIN_KERNEL_CLOCK && !BF60x
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default BFIN_KERNEL_CLOCK_MEMINIT_CALC
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help
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This option allows you to specify Blackfin SDRAM/DDR Timing parameters
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@ -589,6 +622,7 @@ config MAX_VCO_HZ
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default 600000000 if BF548
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default 533333333 if BF549
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default 600000000 if BF561
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default 800000000 if BF609
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config MIN_VCO_HZ
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int
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@ -596,6 +630,7 @@ config MIN_VCO_HZ
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config MAX_SCLK_HZ
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int
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default 200000000 if BF609
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default 133333333
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config MIN_SCLK_HZ
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@ -38,7 +38,7 @@ extern unsigned long get_sclk(void);
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#ifdef CONFIG_BF60x
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extern unsigned long get_sclk0(void);
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extern unsigned long get_sclk1(void);
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extern unsigned long get_dramclk(void);
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extern unsigned long get_dclk(void);
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#endif
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extern unsigned long sclk_to_usecs(unsigned long sclk);
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extern unsigned long usecs_to_sclk(unsigned long usecs);
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@ -892,9 +892,6 @@ void __init setup_arch(char **cmdline_p)
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{
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u32 mmr;
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unsigned long sclk, cclk;
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#ifdef CONFIG_BF60x
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struct clk *clk;
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#endif
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native_machine_early_platform_add_devices();
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@ -959,24 +956,8 @@ void __init setup_arch(char **cmdline_p)
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~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
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#endif
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#ifdef CONFIG_BF60x
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clk = clk_get(NULL, "CCLK");
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if (!IS_ERR(clk)) {
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cclk = clk_get_rate(clk);
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clk_put(clk);
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} else
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cclk = 0;
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clk = clk_get(NULL, "SCLK0");
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if (!IS_ERR(clk)) {
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sclk = clk_get_rate(clk);
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clk_put(clk);
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} else
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sclk = 0;
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#else
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cclk = get_cclk();
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sclk = get_sclk();
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#endif
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if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
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panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
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@ -1062,8 +1043,13 @@ void __init setup_arch(char **cmdline_p)
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printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
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#ifdef CONFIG_BF60x
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printk(KERN_INFO "Processor Speed: %lu MHz core clock, %lu MHz SCLk, %lu MHz SCLK0, %lu MHz SCLK1 and %lu MHz DCLK\n",
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cclk / 1000000, sclk / 1000000, get_sclk0() / 1000000, get_sclk1() / 1000000, get_dclk() / 1000000);
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#else
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printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
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cclk / 1000000, sclk / 1000000);
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#endif
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setup_bootmem_allocator();
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@ -351,7 +351,7 @@ static struct clk dclk = {
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.rate = 500000000,
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.mask = CGU0_DIV_DSEL_MASK,
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.shift = CGU0_DIV_DSEL_SHIFT,
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.parent = &pll_clk,
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.parent = &sys_clkin,
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.ops = &sys_clk_ops,
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};
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@ -15,10 +15,121 @@
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#include <asm/mem_init.h>
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#include <asm/dpmc.h>
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#ifdef CONFIG_BF60x
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#define CSEL_P 0
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#define S0SEL_P 5
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#define SYSSEL_P 8
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#define S1SEL_P 13
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#define DSEL_P 16
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#define OSEL_P 22
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#define ALGN_P 29
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#define UPDT_P 30
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#define LOCK_P 31
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#define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF)
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#define CGU_DIV_VAL \
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((CONFIG_CCLK_DIV << CSEL_P) | \
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(CONFIG_SCLK_DIV << SYSSEL_P) | \
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(CONFIG_SCLK0_DIV << S0SEL_P) | \
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(CONFIG_SCLK1_DIV << S1SEL_P) | \
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(CONFIG_DCLK_DIV << DSEL_P))
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#define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000)
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#if ((CONFIG_BFIN_DCLK != 125) && \
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(CONFIG_BFIN_DCLK != 133) && (CONFIG_BFIN_DCLK != 150) && \
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(CONFIG_BFIN_DCLK != 166) && (CONFIG_BFIN_DCLK != 200) && \
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(CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250))
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#error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
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#endif
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struct ddr_config {
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u32 ddr_clk;
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u32 dmc_ddrctl;
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u32 dmc_ddrcfg;
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u32 dmc_ddrtr0;
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u32 dmc_ddrtr1;
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u32 dmc_ddrtr2;
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u32 dmc_ddrmr;
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u32 dmc_ddrmr1;
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};
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struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = {
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[0] = {
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.ddr_clk = 125,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20705212,
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.dmc_ddrtr1 = 0x201003CF,
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.dmc_ddrtr2 = 0x00320107,
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.dmc_ddrmr = 0x00000422,
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.dmc_ddrmr1 = 0x4,
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},
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[1] = {
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.ddr_clk = 133,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20806313,
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.dmc_ddrtr1 = 0x2013040D,
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.dmc_ddrtr2 = 0x00320108,
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.dmc_ddrmr = 0x00000632,
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.dmc_ddrmr1 = 0x4,
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},
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[2] = {
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.ddr_clk = 150,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20A07323,
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.dmc_ddrtr1 = 0x20160492,
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.dmc_ddrtr2 = 0x00320209,
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.dmc_ddrmr = 0x00000632,
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.dmc_ddrmr1 = 0x4,
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},
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[3] = {
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.ddr_clk = 166,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20A07323,
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.dmc_ddrtr1 = 0x2016050E,
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.dmc_ddrtr2 = 0x00320209,
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.dmc_ddrmr = 0x00000632,
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.dmc_ddrmr1 = 0x4,
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},
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[4] = {
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.ddr_clk = 200,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20a07323,
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.dmc_ddrtr1 = 0x2016050f,
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.dmc_ddrtr2 = 0x00320509,
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.dmc_ddrmr = 0x00000632,
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.dmc_ddrmr1 = 0x4,
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},
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[5] = {
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.ddr_clk = 225,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20E0A424,
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.dmc_ddrtr1 = 0x302006DB,
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.dmc_ddrtr2 = 0x0032020D,
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.dmc_ddrmr = 0x00000842,
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.dmc_ddrmr1 = 0x4,
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},
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[6] = {
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.ddr_clk = 250,
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.dmc_ddrctl = 0x00000904,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20E0A424,
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.dmc_ddrtr1 = 0x3020079E,
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.dmc_ddrtr2 = 0x0032020D,
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.dmc_ddrmr = 0x00000842,
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.dmc_ddrmr1 = 0x4,
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},
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};
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#else
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#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */
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#define PLL_CTL_VAL \
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(((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
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(PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
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(PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
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#endif
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__attribute__((l1_text))
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static void do_sync(void)
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@ -34,7 +145,43 @@ void init_clocks(void)
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* For example, any automatic DMAs left by U-Boot for splash screens.
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*/
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#if 0
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#ifdef CONFIG_BF60x
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int i, dlldatacycle, dll_ctl;
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bfin_write32(CGU0_DIV, CGU_DIV_VAL);
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bfin_write32(CGU0_CTL, CGU_CTL_VAL);
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while ((bfin_read32(CGU0_STAT) & 0x8) || !(bfin_read32(CGU0_STAT) & 0x4))
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continue;
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bfin_write32(CGU0_DIV, CGU_DIV_VAL | (1 << UPDT_P));
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while (bfin_read32(CGU0_STAT) & (1 << 3))
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continue;
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for (i = 0; i < 7; i++) {
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if (ddr_config_table[i].ddr_clk == CONFIG_BFIN_DCLK) {
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bfin_write_DDR0_CFG(ddr_config_table[i].dmc_ddrcfg);
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bfin_write_DDR0_TR0(ddr_config_table[i].dmc_ddrtr0);
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bfin_write_DDR0_TR1(ddr_config_table[i].dmc_ddrtr1);
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bfin_write_DDR0_TR2(ddr_config_table[i].dmc_ddrtr2);
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bfin_write_DDR0_MR(ddr_config_table[i].dmc_ddrmr);
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bfin_write_DDR0_EMR1(ddr_config_table[i].dmc_ddrmr1);
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bfin_write_DDR0_CTL(ddr_config_table[i].dmc_ddrctl);
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break;
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}
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}
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do_sync();
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while (!(bfin_read_DDR0_STAT() & 0x4))
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continue;
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dlldatacycle = (bfin_read_DDR0_STAT() & 0x00f00000) >> 20;
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dll_ctl = bfin_read_DDR0_DLLCTL();
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dll_ctl &= 0x0ff;
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bfin_write_DDR0_DLLCTL(dll_ctl | (dlldatacycle << 8));
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do_sync();
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while (!(bfin_read_DDR0_STAT() & 0x2000))
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continue;
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#else
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size_t i;
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for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
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struct dma_register *dma = dma_io_base_addr[i];
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@ -92,9 +239,9 @@ void init_clocks(void)
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#ifdef CONFIG_MEM_EBIU_DDRQUE
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bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE);
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#endif
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#endif
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#endif
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do_sync();
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bfin_read16(0);
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#endif
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}
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